PC87591L datasheet(44/437 Pages) NSC

44 / 437 page

2.0 Signal/Pin Description and Configuration (Continued)

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Revision 1.07

2.2.5

Development System Support

Signal

128-Pin

LQFP

176-Pin

LQFP

I/O

Buffer

Type

Power

Well

Description

BE1-0

N/A

121,129

O1/2

VCC Byte Enable bits 1 and 0 on monitor bus

cycles.

BRKL_RSTO N/A

INT/O1/2

VCC Break Line and Reset Out. When the Core

bus is active, the pin is used as a BRKL input.

It Indicates to the core that a breakpoint is

needed once the currently fetched instruction

goes into execution.

When the core bus is not active, the signal is

used as a RSTO output. It indicates to the

system that an internal reset to the core and

its peripherals occurred.

BST2-0

N/A

69,

63-62

OO1/2

VCC Bus Status bits 2-0 on monitor bus cycles. In

DEV environment, these pins allow monitoring

of the external bus cycles. When OBR bit in

BCFG register is set, the internal bus cycles

are also visible on the external bus. See also

Table 41 on page 273.

CBRD

N/A

120

O1/2

VCC Core Bus Read Status on monitor bus

cycles.

Available in all modes. See Section 4.1.9 on

page 81.

PFS

N/A

O1/2

VCC Pipe Flow Status.

PLI

N/A

O1/2

VCC Pipe Long Instruction.

TCK

106

INTS

VCC JTAG Test Clock.

TDI

108

INT

VCC JTAG Test Data In.

TDO

107

O1/2

VCC JTAG Test Data Out.

TINT

105

OD2

VCC JTAG Test Interrupt.

TMS

109

INT

VCC JTAG Test Mode Select.

PC87591L Datasheet(PDF) 44 Page - National Semiconductor (TI)

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