PC87591L datasheet(85/437 Pages) NSC

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4.0 Embedded Controller Modules (Continued)

Revision 1.07

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Static Zone Conﬁguration Register (SZCFGn)

The SZCFGn register (where n = 0, 1 or 2) controls the configuration of zone n. On reset, SZCFGn is initialized to 069F16.

Location: Zone 0 - 00 F98416

Zone 1 - 00 F98616

Zone 2 - 00 F98816

Type: R/W

Bit

9876543210

Name

Reserved

FRE IPRE IPST

Res

WBR BRE

HOLD

WAIT

Reset

0000011010011111

Bit

Description

2-0

WAIT. Number of TIW clock cycles that extend the bus cycle. Ignored when bit 11 (FRE) of this register is set

to 1.

Bits

2 1 0

Number

0 0 0:

None

0 0 1:

One

0 1 0:

Two

0 1 1:

Three

1 0 0:

Four

1 0 1:

Five

1 1 0:

Six

1 1 1:

Seven

4-3

HOLD. Number of Thold clock cycles.

Bits

4 3

Number

0 0:

None

0 1:

One

1 0:

Two

1 1:

Three

BRE (Burst Read Enable). Ignored when bit 11 (FRE) of this register is set to 1.

0: Disabled

1: Enabled

WBR (Wait on Burst Read). Determines if a wait state (TBW) is added on a burst read transaction.

0: No TBW

1: TBW

BW (Bus Width). Sets the external bus width used for the I/O zone. It is initialized during reset to its default

value.

0: 8-bit bus

1: 16-bit bus (default)

Reserved.

IPST (Idle After Bus Cycle). Determines if an idle cycle follows the current bus cycle when the next bus cycle

is in a different zone.

0: No idle cycle inserted

1: Idle cycle inserted

PC87591L Datasheet(PDF) 85 Page - National Semiconductor (TI)

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