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PC87591L Datasheet(PDF) 421 Page - National Semiconductor (TI) |
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PC87591L Datasheet(HTML) 421 Page - National Semiconductor (TI) |
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421 / 437 page ![]() Software for Hardware Interface (Continued) Revision 1.07 421 www.national.com Module Register Name Size Register Address Access Type Value After Reset Comments Shared Memory Host The base address is defined by LDN 0F16 (Section 5.3.8 on page 303). SMIMA0 Byte Offset 0016 Read/Write SMIMA1 Byte Offset 0116 Read/Write SMIMA2 Byte Offset 0216 Read/Write SMIMA3 Byte Offset 0316 Read/Write SMIMD Byte Offset 0416 Read/Write SMHC Byte Offset 0516 Read/Write 0016 SMHST Byte Offset 0616 Varies per bit 0016 SMHAP1 Byte Offset 0716 Varies per bit 0216 SMHAP2 Byte Offset 0816 Varies per bit 0216 SMHSEM Byte Offset 0C16 Varies per bit 0016 MSWC Host Registers The base address is defined by LDN 0416 (Section 5.5.5 on page 323). WK_STS0 Byte Offset 0016 R/W1C 0016 WK_EN0 Byte Offset 0216 Read/Write 0016 WK_CFG Byte Offset 0416 Read/Write 0016 WK_SIGV Byte Offset 0616 Read Only WK_STATE Byte Offset 0716 Read/Write WK_SMIEN0 Byte Bank 2 Offset 1316 Read/Write 0016 WK_IRQEN0 Byte Bank 2 Offset 1516 Read/Write 0016 Host Interface (HI) The base address is defined by LDN 0616 (“Host Addresses” on page 277). DBBOUT Byte Defined in LDN 0616 index 6016, 6116 R STATUS Byte Defined in LDN 0616 index 6216, 6316 R 0016 DBBIN Byte Defined in LDN 0616 index 6016, 6116 W |
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