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Revision 1.07

Power Fail Interrupt Control and Status Register (PFAIL)

The PFAIL register holds the current value of the PFAIL signal and controls the NMI interrupt generation based on a falling

edge of the PFAIL signal. EN and ENLCK are cleared on reset. When writing to this register, all reserved bits must be written

with 0 for the device to function properly.

Location: 00 FE0416

Type: R/W

Interrupt Status Register 0 (ISTAT0)

This register indicates which maskable interrupts are pending regardless of the state of the corresponding IENA bits. ISTAT0

is cleared on reset.

Location: 00 FE0A16

Type: RO

Bit

76543210

Name

Reserved

ENLCK

Reset

xxxx

Bit

Description

EN (PFAIL Interrupt Enable). An NMI interrupt is generated when this bit is set to 1 and the PFAIL signal

changes its value from high to low. The bit is cleared by hardware on reset and whenever the interrupt occurs

(i.e., when EXT bit in NMISTAT register is set). It can be set and cleared by software; however, software can set

this bit only when EXT is cleared. This bit is ignored when ENLCK is set.

0: No NMI interrupt generated

1: NMI interrupt generated

PIN (PFAILPin Value). Contains the current (non-inverted) PFAIL signal value. This bit is read only; data written to

it is ignored.

ENLCK PFAIL Interrupt Enable Lock. When this bit is set to 1, the external PFAIL feature is enabled and

locked; it cannot be cleared by software and can only be cleared by hardware on reset. After setting this bit, an

NMI interrupt is generated every time the PFAIL signal changes its value from high to low. Note that when

ENLCK is set, EN bit is ignored.

0: External PFAIL feature disabled

1: External PFAIL feature enabled and locked

7-3

Reserved.

Bit

9876543210

Name

IST15-0

Reset

000000000000000

Bit

Description

15-0

IST15-0 (Interrupt Status). Each bit indicates if an interrupt event was sent to the ICU; IST15 to IST0

correspond to INT15 to INT0, respectively. Since INT0 is not used, IST0 always reads 0. Each bit is encoded

as follows:

0: Interrupt input to ICU not pending

1: Interrupt input to ICU pending

PC87591L Datasheet(PDF) 102 Page - National Semiconductor (TI)

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