PC87591L datasheet(149/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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Cycle Time Register (CTR)

The CTR register controls the cycle time and duty cycle steps, CTR is set (FF16) on reset.

Location: 00 FD0216

Type: R/W

Duty Cycle Registers 0 to 7 (DCRi)

The DCRi (i = 0 to 7) registers control the duty cycle of PWMi output signal. DCRi is cleared (0016) on reset.

Location: Channel 0 - 00 FD0816

Channel 1 - 00 FD0A16

Channel 2 - 00 FD0C16

Channel 3 - 00 FD0E16

Channel 4 - 00 FD1016

Channel 5 - 00 FD1216

Channel 6 - 00 FD1416

Channel 7 - 00 FD1616

Type: R/W

Bit

76543210

Name

CTR7-0

Reset

11111111

Bit

Description

7-0

Cycle Time Value. The 8-bit down-counter divides the pre-scaler output clock by the number deﬁned by

CTR(7:0) + 1. For example, a value of 0016 results in a divide by 1, a value of FF16 results in a divide by 256.

The contents of this register may be changed only when the PWM module is in Low Power mode. Otherwise,

there may be unpredictable results.

Bit

76543210

Name

DCRi7-0

Reset

00000000

Bit

Description

7-0

Duty Cycle Value. DCRi register deﬁnes the number of clocks for which PWMi is high (from the full cycle of the

PWMi cycle), when Inverse PWMi bit in PWM Polarity register is 0.

If the DCRi value > CTR value, PWMi signal is always low.

If DCRi value == CTR value, PWMi signal is always high.

When Inverse PWMi bit is 1, the value of PWMi is inverse.

PC87591L Datasheet(PDF) 149 Page - National Semiconductor (TI)

PC87591L Datasheet(HTML) 149 Page - National Semiconductor (TI)

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