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TAS5518 Datasheet(PDF) 70 Page - Texas Instruments

Part # TAS5518
Description  TAS5518 8 Channel Digital Audio PWM Processor
PDF  102 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS5518 Datasheet(HTML) 70 Page - Texas Instruments

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Serial Control I2C Register Summary
61
SLES115 — August 2004
TAS5518
I2C
SUBADDRESS
DEFAULT STATE
DESCRIPTION OF CONTENTS
REGISTER FIELDS
TOTAL
BYTES
0x98
8
Channels 1, 2, 3, 4, 5, 6, and 7,
DRC1 energy
DRC1 energy
0.0041579
0x98
8
Channels 1, 2, 3, 4, 5, 6, and 7,
DRC1 (1− energy)
DRC1 (1 energy)
0.9958421
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 threshold (T1) – upper 4 bytes
0x00, 0x00, 0x00, 0x00
0x99
16
,,,,,,
DRC1 threshold T1
DRC1 threshold (T1) – lower 4 bytes
0x0B, 0x20, 0xE2, 0xB2
0x99
16
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 threshold (T2) – upper 4 bytes
0x00, 0x00, 0x00, 0x00
,,,,,,
DRC1 thresholdT2
DRC1 threshold (T2) – lower 4 bytes
0x06, 0xF9, 0xDE, 0x58
Channels 1, 2, 3, 4, 5, 6, and 7
, DRC1 slope k0
DRC1 slope (k0)
0x0F, 0xC0, 0x00, 0x00
0x9A
12
Channels 1, 2, 3, 4, 5, 6, and 7,
DRC1 slope k1
DRC1 slope (k1)
0x0F, 0xC0, 0x00, 0x00
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 slope k2
DRC1 slope (k2)
0x0F, 0x90, 0x00, 0x00
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 offset 1 (O1) – upper 4 bytes
0x00, 0x00, 0xFF, 0xFF
0x9B
16
,,,,,,
DRC1 offset 1
DRC1 offset 1 (O1) – lower 4 bytes
0xFF, 0x82, 0x30, 0x98
0x9B
16
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 offset 2 (O2) – upper 4 bytes
0x00, 0x00, 0x00, 0x00
,,,,,,
DRC1 offset 2
DRC1 offset 2 (O2) – lower 4 bytes
0x01, 0x95, 0xB2, 0xC0
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 attack
DRC1 attack
0x00, 0x00, 0x88, 0x3F
0x9C
16
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 (1− Attack)
DRC1 (1 – Attack)
0x00, 0x7F, 0x77, 0xC0
0x9C
16
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 Delay
DRC1 delay
0x00, 0x00, 0x00, 0xAE
Channels 1, 2, 3, 4, 5, 6, and 7
DRC1 (1− Delay)
DRC1 (1 – Delay)
0x00, 0x7F, 0xFF, 0x51
0x9D
8
Ch 8 DRC2 energy
DRC2 energy
0x00, 0x00, 0x88, 0x3F
0x9D
8
Ch 8 DRC2 (1− Energy)
DRC2 (1 – Energy)
0x00, 0x7F, 0x77, 0xC0
CH 8 DRC2 threshold T1
DRC2 threshold (T1) – upper 4 bytes
0x00, 0x00, 0x00, 0x00
0x9E
16
CH 8 DRC2 threshold T1
DRC2 threshold (T1) – lower 4 bytes
0x0B, 0x20, 0xE2, 0xB2
0x9E
16
CH 8 DRC2 threshold T2
DRC2 threshold (T2) – upper 4 bytes
0x00, 0x00, 0x00, 0x00
CH 8 DRC2 threshold T2
DRC2 threshold (T2) – lower 4 bytes
0x06, 0xF9, 0xDE, 0x58
Ch 8 DRC2 slope k0
DRC2 slope (k0)
0x00, 0x40, 0x00, 0x00
0x9F
12
Ch 8 DRC2 slope k1
DRC2 slope (k1)
0x0F, 0xC0, 0x00, 0x00
0x9F
12
Ch 8 DRC2 slope k2
DRC2 slope (k2)
0x0F, 0x90, 0x00, 0x00
Ch 8 DRC2 offset 1
DRC2 offset (O1) – upper 4 bytes
0x00, 0x00, 0xFF, 0xFF
0xA0
16
Ch 8 DRC2 offset 1
DRC2 offset (O1) – lower 4 bytes
0xFF, 0x82, 0x30, 0x98
0xA0
16
Ch 8 DRC2 offset 2
DRC2 offset (O2) – upper 4 bytes
0x00, 0x00, 0x00, 0x00
Ch 8 DRC2 offset 2
DRC2 offset (O2) – lower 4 bytes
0x01, 0x95, 0xB2, 0xC0
Ch 8 DRC2 attack
DRC 2 attack
0x00, 0x00, 0x88, 0x3F
0xA1
16
Ch 8 DRC2 (1− Attack)
DRC2 (1 – Attack)
0x00, 0x7F, 0x77, 0xC0
0xA1
16
Ch 8 DRC2 Delay
DRC2 delay
0x00, 0x00, 0x00, 0xAE
Ch 8 DRC2 (1− Delay)
DRC2 (1 – Delay)
0x00, 0x7F, 0xFF, 0x51
0xA2
8
DRC bypass 1
Channel 1 DRC1 bypass coefficient
1.0
0xA2
8
DRC inline 1
Channel 1 DRC1 inline coefficient
0.0
0xA3
8
DRC bypass 2
Channel 2 DRC1 bypass coefficient
1.0
0xA3
8
DRC inline 2
Channel 2 DRC1 inline coefficient
0.0



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