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TAS5518 Datasheet(PDF) 87 Page - Texas Instruments

Part # TAS5518
Description  TAS5518 8 Channel Digital Audio PWM Processor
PDF  102 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS5518 Datasheet(HTML) 87 Page - Texas Instruments

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Serial Control Interface Register Definitions
78
SLES115 — August 2004
TAS5518
6.22 DRC1 Data Registers (0x98 – 0x9C)
DRC1 applies to channels 1, 2, 3, 4, 5, 6, and 7.
Table 6−24. DRC1 Data Registers
I2C
SUBADDRESS
TOTAL
BYTES
REGISTER NAME
DESCRIPTION OF CONTENTS
DEFAULT STATE
0x98
8
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Energy
U (31:28), E (27:24), E (23:16), E (15:8), E (7:0)
0x00, 0x00, 0x88, 0x3F
0x98
8
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 (1− Energy)
U (31:28), 1−E (27:24), 1−E (23:16), 1−E (15:8),
1−E (7:0)
0x00, 0x7F, 0x77, 0xC0
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Threshold Upper 16 bits
(T1)
U (31:24), U (23:16), T1 (15:8), T1 (7:0)
0x00, 0x00, 0x00, 0x00
0x99
16
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Threshold Lower 32 bits
(T1)
T1 (31:24), T1 (23:16), T1 (15:8), T1 (7:0)
0x0B, 0x20, 0xE2, 0xB2
0x99
16
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Threshold
Upper 16 bits (T2)
U (31:24), U (23:16), T2 (15:8), T2 (7:0)
0x00, 0x00, 0x00, 0x00
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Threshold
Lower 32 bits (T2)
T2 (31:24), T2 (23:16), T2 (15:8), T2 (7:0)
0x06, 0xF9, 0xDE, 0x58
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 slope (k0)
U (31:28), k0 (27:24), k0 (23:16), k0 (15:8),
k0 (7:0)
0x00, 0x40, 0x00, 0x00
0x9A
12
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 slope (k1)
U (31:28), k1 (27:24), k1 (23:16), k1 (15:8),
k1 (7:0)
0x0F, 0xC0, 0x00, 0x00
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 slope (k2)
U (31:28), k2 (27:24), k2 (23:16), k2 (15:8),
k2 (7:0)
0x0F, 0x90, 0x00, 0x00
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Offset 1 Upper 16 bits
(O1)
U (31:24), U (23:16), O1 (15:8), O1 (7:0)
0x00, 0x00, 0xFF, 0xFF
0x9B
16
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Offset 1 Lower 32 bits
(O1)
O1 (31:24), O1 (23:16), O1 (15:8), O1 (7:0)
0xFF, 0x82, 0x30, 0x98
0x9B
16
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Offset 2 Upper 16 bits
(O2)
U (31:24), U (23:16), O2 (15:8), O2 (7:0)
0x00, 0x00, 0x00, 0x00
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Offset 2 Lower 32 bits
(O2)
O2 (31:24), O2 (23:16), O2 (15:8), O2 (7:0)
0x01, 0x95, 0xB2, 0xC0
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Attack
U (31:28), A (27:24), A (23:16), A (15:8), A (7:0)
0x00, 0x00, 0x88, 0x3F
0x9C
16
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 (1− Attack)
U (31:28), 1−A (27:24), 1−A (23:16), 1−A (15:8),
1−A (7:0)
0x00, 0x7F, 0x77, 0xC0
0x9C
16
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 Decay
U (31:28), D (27:24), D (23:16), D (15:8), D (7:0)
0x00, 0x00, 0x00, 0xAE
Channel 1, 2, 3, 4, 5, 6, and 7
DRC1 (1− Decay)
U (31:28), 1−D (27:24), 1−D (23:16), 1−D (15:8),
1−D (7:0)
0x00, 0x7F, 0xFF, 0x51



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