LM4931 datasheet(21/47 Pages) NSC

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Clock Divider Configuration Registers

This register is used to control the multiplexers in the clock module.

DEFAULT CHART FOR CLK_MUX (08h)

DATA BIT

DEFAULT

CLK_MUX (08h) (SET = LOGIC 1, CLEAR = LOGIC 0)

Address

Description

PLL_INPUT

Programs the PLL input multiplexer to select. (Note 12)

PLL_INPUT

PLL Input Source

MCLK

2S Input Clock

FAST_CLOCK

If set the master clock is divided by two, for example allowing for a

24.576MHz or PCI clock to be used. (Note 12, 15)

FAST_CLOCK

MCLK Frequency

Normal

Divided by 2

AUDIO_CLK_SEL

Selects which clock is passed to the audio sub-system: (Note 12)

AUDIO_CLK_SEL

Audio Sub-system

Input Source

PLL Output

MCLK / MCLK/2

VOICE_CLK_SEL

Selects which clock is passed to the voice sub-system: (Note 12)

VOICE_CLK_SEL

Audio Sub-system

Input Source

PLL Output

MCLK / MCLK/2

PLL_DISABLE

Powers down the PLL if it is not required.

6:5

Q_DIV

Programs the Q divider (divides from the PLL output frequency of

12.288MHz).

6:5

Divide Value

12 (1.024MHz/8kHz)

8 (1.536MHz/12kHz)

6 (2.048MHz/16kHz)

4 (3.072MHz/24kHz)

RSVD

RESERVED (Note 14)

Note 15: For inputs greater than 50Mhz, the input clock divider FAST_CLOCK should be set.

LM4931 Datasheet(PDF) 21 Page - National Semiconductor (TI)

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