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LM4931 Datasheet(PDF) 44 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # LM4931
Description  Audio Subsystem with Mono High Efficiency Loudspeaker and Stereo Headphone Amplifiers
PDF  47 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM4931 Datasheet(HTML) 44 Page - National Semiconductor (TI)

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Application Information (Continued)
toggled into and out of rapidly and is ideal for saving power
whenever continuous audio is not a requirement. All other
part functions are suspended.
Mono Speaker Mode (0010b)
Part is active. All analog outputs are biased. Audio from the
voiceband codec is routed to the mono speaker out. Stereo
headphone out is muted.
Headphone Call Mode (0011b)
Part is active. All analog outputs are biased. Audio from
voiceband codec is routed to the stereo headphones. Both
left and right channels are the same. Mono speaker out is
muted.
Conference Call Mode (0100b)
Part is active. All analog outputs are biased. Audio from the
voiceband codec is routed to the mono speaker out and to
the stereo headphones.
L+R Mixed to Mono Speaker (0101b)
Part is active. All analog outputs are biased. Full-range audio
from the 18bit/48kHz audio DAC is mixed together and
routed to the mono speaker out. Stereo headphones are
muted.
Headphone Stereo Audio (0110b)
Part is active. All analog outputs are biased. Full-range audio
from the 18bit/48kHz audio DAC is sent to the stereo head-
phone jack. Each channel is heard discretely. The mono
speaker is muted.
L+R Mixed to Mono Speaker + Stereo Headphone
Audio (0111b)
Part is active. All analog outputs are biased. Full-range audio
from the 18bit/48kHz audio DAC is sent discretely to the
stereo headphone jack and also mixed together and sent to
the mono speaker out.
Mixed Mode (1000b)
Part is active. All analog outputs are biased. This provides
one channel (the left channel) of full range audio to the mono
speaker out. Audio from the voiceband codec is then sent to
the stereo headphones, the same on each channel.
Mixed Mode (1001b)
Part is active. All analog outputs are biased. Mixed voice-
band and full-range audio (left channel only) is sent to the
mono speaker out. Audio from the voiceband codec only is
sent to the stereo headphones, the same on each channel.
Mixed Mode (1010b)
Part is active. All analog outputs are biased. Audio from the
voiceband codec is sent to the mono speaker out. The left
channel only of the full range audio is then sent to both the
left and right channels of the stereo headphone out.
REGISTERS
The LM4931 starts on power-up with all registers cleared in
Powerdown mode. Powerdown mode is the recommended
time to make setup changes to the digital interfaces (PCM
bus, I
2S bus). Although the configuration registers can be
changed in any mode, changes made during Standby or
Powerdown prevent unwanted audio artifacts that may occur
during rapid mode changes with the outputs active. The
LM4931 also features a soft reset. This reset is enabled by
setting bit 4 of the BASIC_CONFIG (00h) register. DAC
dither may also be controlled in this register (bit 5).
The VOICE_CONFIG (01h) register is used to set various
configuration parameters on the voiceband and full-range
audio codecs. SIDETONE_ATTEN (bits 3:0) refers to the
level of signal from the MIC input that is fed back into the
analog audio output path (commonly used in headphone
applications and killed in hands-free applications). Setting
the AUTOSIDE bit (bit 4) automatically mutes the sidetone in
voice over mono speaker modes so feedback isn’t an issue.
Dither for the voice ADC and DAC may be disabled by
setting bits 6 or 7, respectively. Bit 5 is reserved.
The MIC_GAIN (02h) register provides for microphone
preamplifier gains of 6dB to 36dB in 2dB steps (bits 3:0). A
quick mute bit is provided for the mic (bit 4) as well as a bit
to disable the high-pass filter on the voice ADC, allowing
wider bandwidth usage through the microphone input.
The HP_GAIN (03h) register provides settings for head-
phone control. Bits 4:0 set the gain of the headphone output
from –46.5dB to 0dB in 1.5dB steps. A quick mute bit is also
provided (bit 5). Additionally, the LM4931 may be configured
to react to a high or low HP_SENSE voltage (bit 6) and may
also provide this output on the GPIO pin in either positive or
negative form (bit 7). This will only be seen on the GPIO
output if it is configured to show HP_CONNECTED as de-
scribed in the GPIO section.
The LS_GAIN (04h) register is used to set the mono class D
loudspeaker gain. Bits 4:0 set this from –34.5dB to +12dB in
1.5dB steps. A quick mute (bit 5) is provided as well as an
auto-mute bit (bit 6) that, if set, automatically mutes the
loudspeaker when headphone sense detects that head-
phones have been connected. A powerdown bit (bit 7) is also
provided to independently shutdown just the class D ampli-
fier.
CLK_MUX (08h) is the clock divider register. Bit 0 sets the
PLL input source. When clear, MCLK is used, when set, the
I
2S input clock is used. Bit 1 gives a divide by 2 for usage
with a faster MCLK (like 24.576MHz). Bit 2 selects which
clock is passed to the full range audio subsystem. If clear,
the PLL output is used. If set, MCLK (or MCLK/2 if set) is
used directly. Bit 3 does the same for the voice codec
subsystem. If clear, the PLL output is used. If set, MCLK or
MCLK/2 is used. Bit 4 powers down the PLL (if not needed).
Bits 6:5 program the Q divider, that can be further used to
divide down the PLL output frequency. Bit 7 is reserved.
The INTERFACES (09h) register controls all the digital in-
terface configurations. This may be used to set the PCM
configuration and I
2S configuration as stated above in the
PCM Bus Interface and I
2S Bus Interface sections. Bits 6 is
reserved for test modes.
The PMC_CONFIG (0Ah) register controls various power
management responsibilities including bypass capacitor size
(bits 2:1). Zero crossing disable (bit 0) is also provided to
allow the LM4931 to change modes regardless of zero
crossing detect status. If set, the LM4931 will change modes
immediately without waiting for the outputs to cross zero.
Bits 6 is reserved.
PLL Registers
The PLL will accept incoming clock frequencies from 10MHz
to 25MHz. However, since the control clocks, PCM clocks,
and I
2S clocks all operate at fixed, defined frequencies the
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