LM4931 datasheet(42/47 Pages) NSC

42 / 47 page

Application Information (Continued)

LM4931ITL DEMO BOARD OPERATION

The LM4931ITL demo board is a complete evaluation plat-

form, designed to give easy access to the control pins of the

part and comprises all the necessary external passive com-

ponents. Besides the separate analog (JP8), digital (JP7),

PLL (JP9) and Loudspeaker (JP10) supply connectors, the

board features seven other major input and control blocks:

an SPI/I

2C compatible selectable interface bus (JP11) for the

control lines, a PCM interface bus (JP12) for voiceband

digital audio, an I

2S interface bus (JP13) for full-range digital

audio, an analog mic jack input (JP1) for connection to an

external microphone, a high efficiency class D BTL mono

output (JP5) for connection to an external speaker, a stereo

headphone output (JP15 or P1), and an external MCLK input

(JP3) for use in place of the crystal on the demoboard.

SPI/I

2C Interface Bus (JP11)

This is the main control bus for the LM4931. This interface

may either be configured as a two-wire, I

2C compatible

interface by setting MODE = 0 (S1 = IN) or a three-wire SPI

interface by setting MODE = 1 (S1 = OUT).

2C Compatible Mode (MODE = 0)

The two-wire I

2C compatible interface consists of an SDA

line (data) and SCL line (clock). Each transmission from the

baseband controller to the LM4931 is given MSB first and

must follow the timing intervals given in the Electrical Char-

acteristics section of the datasheet to create the start and

stop conditions for a proper transmission. The start condition

is detected if SCL is high on the falling edge of SDA. The

stop condition is detected if SCL is high on the rising edge of

SDA. Repeated start signals are handled correctly. Data is

then transmitted as shown in Figure 3 for the Two Wire I

Compatible Interface. After the start condition has been

achieved the chip address is sent, followed by a set write bit,

wait for ack (SDA will be pulled low by LM4931), data bits

15-8, wait for ACK (SDA will be pulled low by LM4931), data

bits 7-0, wait for ACK (SDA will be pulled low by LM4931)

and finally the stop condition is given.

This same sequence follows for any I

2C control bus trans-

mission to the LM4931. The chip address is hardwire se-

lected by the ADDR Select pin (JP11, pin 4) which may be

software enabled high or low with the LM4931 demonstra-

tion control software. If ADDR is low, then the chip address is

set to 0010000b. If ADDR is high, the address is set to

1110000b. The 11 control registers are shown on page 13 in

the System Control Table. Data is sampled only if the

address is in range and the R/W bit is clear. Data for each

datasheet.

Pull-up resistors are required to achieve reliable operation.

10k

Ω pull-up resistors on the SDA and SCL lines achieves

best results when used with National’s parallel-to-serial in-

terface board. Lower value pull-up resistors will decrease the

rise and fall times on the bus which will in turn decrease

susceptibility to bus noise that may cause a false trigger. The

cost comes at extra current use. Control bus reliability will

thus depend largely on bus noise and may vary from design

to design. Low noise is critical for reliable operation.

SPI Mode (MODE = 1)

The SPI interface consists of three lines: the serial data input

pin (SDI), the clock input pin (SCK), and the SPI enable pin

(ENB).The serial data bits are organized into two fields of 8

bit data as shown on Figure 2 in the Three Wire, SPI

Interface timing diagram. The first 8 bits corresponds to the

page 13. The second 8 bits contains the data to write to the

desired control register. These fields are transmitted subse-

quently to form a 16 bit word. For each SPI transfer, ENB is

lowered and the data bits are written to the SDI pin with the

most significant bit (MSB) first. All serial data are sampled at

the rising edge of the SCK signal. Once all the data bits have

been sampled, ENB transitions from logic-high to logic-low

to complete the SPI sequence. All 16 bits must be received

before any data latch can occur. Any excess CLK and DATA

transitions will be ignored after the sixteenth rising clock

edge has occurred. For any data sequence longer than 16

bits, only the first 16 bits will get loaded into the shift register

and the rest of the bits will be disregarded.

SPI Operational Requirements

1. The data bits are transmitted with the MSB first.

2. The maximum clock rate is 4MHz for the SCK pin.

3. SCK must remain logic-high for at least 500ns (t

SPICH )

after the rising edge of SCK, and SCK must remain logic-low

for at least 500ns (t

SPICL) after the falling edge of SCK.

4. The serial data bits are sampled at the rising edge of SCK.

Any

transition

SDI

must

occur

least

100ns

SPISETHOLDD) before the rising edge of SCK. Also, any

transition on SDI must occur at least 100ns (t

SPISETD) after

the rising edge of SCK and stabilize before the next rising

edge of SCK.

5. ENB should be logic-low only during serial data transmis-

sion.

6. ENB must be logic-low at least 100ns (t

SPISETENB ) before

the first rising edge of SCK, and ENB has to remain logic-low

at least 100ns (t

SPIHOLDENB) after the sixteenth rising edge

of SCK.

7. If ENB remains logic-high for mtore than 10ns before all

16 bits are transmitted then the data latch will be aborted.

8. If ENB is logic-low for more than 16 SCK pulses then only

the first 16 data bits will be latched and activated when ENB

transitions to logic-high.

9. ENB must remain logic-low for at least 100ns (t

SPIHOLD-

ENB

) to latch in the data.

10. Coincidental rising or falling edges of SCK and ENB are

not allowed. If SCK is to be held logic-high after the data

transmission, the falling edge of SCK must occur at least

100ns before ENB transitions to logic-low for the next set of

data.

LM4931 Evaluation Software

The LM4931 demoboard can be easily evaluated with the

accompanying LM4931 Evaluation Software. The Win-

dows 95/98/2000/NT/XP compatible software is a GUI that

allows easy access to all the I

2C/SPI internal registers of the

device. The GUI controls the PC parallel port to deliver the

appropriate I

2C/SPI commands via the National Semicon-

ductor I

2C/SPI Interface Card, in order to properly program

the LM4931.

PCM Bus Interface (JP12)

PCM_SDO, PCM_SYNC, PCM_SDI, and PCM_CLK form

the PCM interface bus for simple communication with most

baseband ICs with voiceband communications and follow

the PCM-1900 communications standard. The PCM inter-

face features a frame length of 16 bits, A-law and u-law

companded, linear mode, short or long frame sync, an

LM4931 Datasheet(PDF) 42 Page - National Semiconductor (TI)

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