The voice codec operates at 128*fs, so it requires a 1.024MHz clock to operate on 8kHz data. The Audio DAC also operates at

128*fs, i.e. 6.144MHz for 48kHz data, 5.6448MHz for 44.1kHz data etc. It is expected that the PLL is used to drive the audio

system unless a 12.288MHz or 24.576MHz (AC’97) master clock is supplied and the sample rate is always 48kHz, in which case

the PLL can be bypassed to reduce power.

The voice codec is always driven from the divided down clock from the PLL output or a divided down version of the master clock.

When using the voice codec for 8kHz operation, program the PLL as you would for 48kHz operation and use Q to divide by

(2*FSaudio/FSvoice).

The PLL can also use the I2S clock input as a source. In this case, the audio DAC uses the clock from the output of the PLL and

the voice codec either uses a divided by 6 clock or a divided version of the MCLK pin.

MCLK must be less than or equal to 50MHz if the input divider is to be used, otherwise MCLK can be any frequency up to 25MHz.

The comparison frequency after the M divider should be less than 5MHz

20100964

FIGURE 5.

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