MCP3910 datasheet(34/86 Pages) MICROCHIP

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MCP3910

DS20005116B-page 34

 2012-2014 Microchip Technology Inc.

5.4

SINC3 + SINC1 Filter

The decimation filter present in all channels of the

MCP3910

cascade

two

sinc

filters

(SINC3+SINC1): a third-order sinc filter with a

decimation ratio of OSR3, followed by a first-order sinc

filter with a decimation ratio of OSR1 (moving average

of OSR1 values). Figure 5-3 represents the decimation

filter architecture.

FIGURE 5-3:

MCP3910 Decimation Filter Block Diagram.

Equation 5-1 calculates the filter z-domain transfer

function.

EQUATION 5-1:

SINC FILTER TRANSFER

FUNCTION

Equation 5-2 calculates the settling time of the ADC as

a function of DMCLK periods.

EQUATION 5-2:

The SINC1 filter following the SINC3 filter is only

enabled for the high OSR settings. This SINC1 filter

provides additional rejection at a low cost with little

modification to the -3 dB bandwidth. The resolution

(number of significant bits) of the digital filter is 24 bit

maximum for any OSR and data format choice. The

resolution depends only on the OSR<2:0> settings in

the CONFIG0 register per Table 5-4. Once the OSR is

chosen, the resolution is fixed and the output code

respects

the

data

format

defined

the

WIDTH_DATA<1:0> setting in the STATUSCOM

The gain of the transfer function of this filter is 1 at each

multiple of DMCLK (typically 1 MHz), so a proper anti-

aliasing filter must be placed at the inputs. This will

attenuate the frequency content around DMCLK and

keep the desired accuracy over the baseband of the

converter. This anti-aliasing filter can be a simple, first-

order RC network, with a sufficiently low-time constant

to generate high rejection at the DMCLK frequency

Any unsettled data is automatically discarded to avoid

data corruption. Each data ready pulse corresponds to

fully settled data at the output of the decimation filter.

The first data available at the output of the decimation

filter is present after the complete settling time of the

filter (see Table 5-4). After the first data has been

processed, the delay between two data ready pulses is

one DRCLK period. The data stream from input to

output is delayed by an amount equal to the settling

time of the filter (which is the group delay of the filter).

The resolution achievable, the -3 dB bandwidth and the

settling time at the output of the decimation filter (the

output of the ADC), are dependent on the OSR of each

sinc filter and are summarized in Table 5-4.

Modulator

Output

SINC

Decimation Filter

Output

OSR3

OSR1

16 (WIDTH = 0)

24 (WIDTH = 1)

Decimation Filter

OSR1 =



- OSR

–





OSR

1z 1

–



3

----------------------------------------------

- OSR

OSR



–





OSR

- OSR

–







---------------------------------------------------------



Where z

EXP 2

 jf



 DMCLK







Sett lingTi me DMCLKperiods

 3OSR



OSR

–

 OSR



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