ML7344CE datasheet(119/154 Pages) LAPIS

119 / 154 page

FEDL7344C/E/J-05

ML7344C/E/J

119/154

(2) FIFO mode (less than 64 byte)

FIFO mode can be selected by RXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(7-6)])=0b00. After SyncWord

detection, RX data will be stored into the RX_FIFO. Upon Data RX completion interrupt (INT[8] group2)

occurs, the host will read RX data from [RD_FIFO:B0 0x7F] registers. If CRC errors interrupt (INT[9] group2)

is generated, the next packet can be ready to receive without reading all current RX data by setting

STATE_CLR1 [STATE_CLR: B0 0x16(1)](RX FIFO pointer clear). If FIFO-Full trigger and FIFO-Empty

trigger are not used, please set 0b0 to both RXFIFO_THRH_EN([RXFIFO_THRH: B0 0x19(7)]) and

RXFIFO_THRL_EN([RXFIFO_THRH: B0 0x1A(7)]) .

START

RX_ON issue *1

[RF_STATUS: B0 0x0B]

Yes

Next packet to be received?

Yes

TRX_OFF issue

[RF_STATUS: B0 0x0B]

Read RX data

[RD_FIFO:B0 0x7F]

TX?

Yes

INT[8] clear

[INT_SOURCE_GRP2: B0 0x0E]

RX FIFO trigger level setting

[RXFIFO_THRH: B0 0x19]=0x00

[RXFIFO_THRL: B0 0x1A]=0x00

CRC error (INT[9])?

[INT_SOURCE_GRP2] B0 0x0E(1)]

Yes

RX completion (INT[8])?

[INT_SOURCE_GRP2] B0 0x0E(0)]

To RF state transition wait flow

Set TX_ON after RX completion?

[RF_STATUS_CTRL:B0 0x0A]

Yes

Set TRX_OFF/SLEEP after RX completion?

[RF_STATUS_CTRL:B0 0x0A]

Yes

TX_ON issue

[RF_STATUS: B0 0x0B]

To RF state transition wait

flow and TX flow

INT[9] clear

[INT_SOURCE_GRP2: B0 0x0E]

RX FIFO pointer clear

[STATE_CLR: B0 0x16(1)]

*1 At lease following 2 interrupts in the group 2

should be un-masked for data receiving.

INT[8]: RX completion interrupt

INT[15]: Sync error interrupt

ML7344CE Datasheet(PDF) 119 Page - LAPIS Semiconductor Co., Ltd.

ML7344CE Datasheet(HTML) 119 Page - LAPIS Semiconductor Co., Ltd.

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