MICRF507 datasheet(17/47 Pages) MICREL

17 / 47 page

Micrel, Inc.

MICRF507

October 2, 2013

Revision 2.2

An external reference clock, when used instead of a

crystal, should be applied to pin 24 (XTALOUT) with pin

23 (XTALIN) not connected. To maintain proper DC

biasing within the chip, use AC-coupling between the

external reference and the XTALOUT-pin.

BITSYNC_CLK (Receiver Bit Synchronization Clock)

The

frequency

the

bit

synchronization

clock

fBITSYNC_CLK,

is a function of the crystal oscillator

frequency fXCO and the values of the register fields

Refclk_K and BitSync_clkS:

)

XCO

BITSYNC_CL

Refclk_K

BitSync_cl

The bit synchronizer uses a clock that needs to be

programmed to 16 times the actual bit rate. As an

example, a bit rate of 20kbps needs a bit synchronizer

clock with frequency of 320kHz. Refer to Figure 9 and

“Data Interface and Bit Synchronization” section for more

details.

BITRATE_CLK (Transmitter Bit Rate Clock)

The frequency fBITRATE_CLK of BITRATE_CLK is a function

of the crystal oscillator frequency fXCO and the values of

the register fields Refclk_K and BitRate_clkS:

kS)

BitRate_cl

XCO

BITRATE_CL

Refclk_K

In transmit mode, when Sync_en = 1, BITRATE_CLK

appears on the DATACLK pin. Its frequency is equal to

the bit rate. Example; a bit rate of 20 kbit/sec requires an

fBITRATE_CLK of 20kHz. Refer to Figure 9 and the “Data

Interface and Bit Synchronization” subsection for more

details.

MODULATOR_CLK (VCO Modulator Clock)

The frequency fMOD_CLK of MODULATOR_CLK is a

function of the crystal oscillator frequency fXCO and the

values of the register fields Refclk_K and Mod_clkS:

)

XCO

MOD_CLK

Refclk_K

Mod_clkS

The modulator clock is used if VCO modulation method

is selected. Set the modulator clock frequency to either

8x or 16x the bit rate. See “VCO Modulation and the

Modulator” subsection for more information.

BitRate_clkS[2:0]

BitSync_clkS[2:0]

Mod_clkS[2:0]

Corresponding Clock

Frequency

(fXCO is crystal frequency)

000

fXCO/(128xRefClk_K)

001

fXCO/(64xRefClk_K)

010

fXCO/(32xRefClk_K)

011

fXCO/(16xRefClk_K)

100

fXCO/(8xRefClk_K)

101

fXCO/(4xRefClk_K)

110

fXCO/(2xRefClk_K) (*)

111

fXCO /RefClk_K (*)

(*) Can not be used as BitRate_clk.

Table 5. Generation of Bitrate_clk, BitSync_clk

and Mod_clk

Data Interface and Bit Synchronization

Transmitted and received data bits are coupled to the

MICRF507 serially through the Data Interface. This Data

Interface consists of the DATAIXO and DATACLK pins.

This is a separate interface from the Control Interface

(CS, IO, and SCLK), for which see Control (3-wire)

Interface.

Figure 9 shows the data interface circuitry aboard the

MICRF507. DATAIXO is an input during transmission,

whereas during reception a driver is enabled and it

becomes an output. DATACLK is always an output.

A rule that applies when using VCO modulation is: after

commanding the MICRF507 to enter transmit mode, the

microcontroller shall tri-state the driver connected to

DATAIXO

leave

that

floating

until

the

microcontroller

begins

sending

data.

See

“Mode

Transitions” section for more details.

The data interface can be programmed for synchronous

and non-synchronous operation according to the setting

of the Sync_en bit; see Table 7.

MICRF507 Datasheet(PDF) 17 Page - Micrel Semiconductor

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