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MICRF507 Datasheet(PDF) 37 Page - Micrel Semiconductor |
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MICRF507 Datasheet(HTML) 37 Page - Micrel Semiconductor |
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37 / 47 page ![]() Micrel, Inc. MICRF507 October 2, 2013 37 Revision 2.2 Layout Considerations To ensure the best RF performance, a carefully planned layout is essential. Grounding, RF path geometry, supply routing, and layer definition all play a role in an optimal design. These are discussed below, and a recommended layout can be found on the Micrel website at: www.micrel.com. Layer Definition A typical MICRF507 PCB design consists of four layers, with the following stack-up: Layer1 – Component and RF routing Layer2 – Ground Layer3 – VDD Routing Layer 4 – Non-RF Routing While not the only acceptable definition, this example provides a good foundation for the general techniques discussed below. Grounding Design the layout to provide the shortest possible return path for signals and noise sources. Place ground vias close to all critical items such as ground pins on the RF IC, decoupling capacitors, and matching components. RF Traces The ANT pin impedance is approximately 50 Ω. To minimize reflection due to impedance mismatch, RF traces should be a controlled impedance of 50 Ω as well. Refer to the Micrel Development Board layout, or a transmission line impedance calculator to verify a specific geometry’s characteristic impedance. Supply Routing The radio system is sensitive to supply noise and signals coupled from one section to another. Routing the supply lines on an internal layer (below the ground layer) separates them from potential noise sources such as the reference oscillator, PA, charge pump, etc. Route supplies separately and place bypass capacitors as close as possible to the associated pin. PLL Loop Filter Place loop filter components close to each other and near pins 27 and 29. Connection of the loop filter to VDD should occur very close to VCOVDD, pin 31. Avoid routing potentially noisy busses or traces near the loop filter. |
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