MICRF507 datasheet(19/47 Pages) MICREL

19 / 47 page

Micrel, Inc.

MICRF507

October 2, 2013

Revision 2.2

Mode

Sync_en

DATACLK

DATAIXO

Direction

Signal

Direction

Signal/Function

Transmit

Output

Input

Modulates carrier directly

(asynchronously)

Output

BitRate clock

Input

Sampled at rising edge of BitRate

clock; latched output modulates

carrier

Receive

Output

Raw output from demodulator

Output

Clock recovered by bit

synchronizer

Output

Filtered and latched demodulator

output; transitions occur at rising

edge of DATACLK

Table 8. Synchronizer Mode and Data Interface

In sync mode (Sync_en bit set to 1), the transmitted bit

stream is clocked with the precision of the MICRF507’s

crystal

oscillator,

which

relaxes

timing

accuracy

requirements on the data source. During reception, the

synchronizer ensures that transitions of DATAIXO occur

only at rising edges of DATACLK, without edge jitter or

internal glitches. Receiver sensitivity values given in the

Electrical Characteristics table are measured with Sync_en

= 1; with Sync_en = 0, as much as 3-6 dB of sensitivity

could be lost.

Sync_en = 0

When Sync_en = 0, the input signal at DATAIXO

modulates the transmitter directly during transmission and

the output signal from DATAIXO is the raw demodulator

output. DATACLK remains fixed at a logic low level during

both transmission and reception.

Sync_en = 1

During transmission when Sync_en = 1 the data bit stream

entering DATAIXO is buffered with a flip-flop strobed at the

rising edge of BITRATE_CLK, and the output of the flip-

flop modulates the transmitter. BITRATE_CLK is brought

out at the DATACLK output. Figure 10 shows the

relationship of DATACLK and DATAIXO transitions.

Figure 10. Data Interface in Transmit Mode

During reception, the bit synchronizer recovers the

received signal’s clock. This recovered clock strobes a flip-

flop that samples in mid-bit-period the demodulated and

filtered bit stream. The DATACLK output brings out the

recovered clock. DATAIXO (an output during reception)

brings out the synchronized data stream, which has its

transitions at rising edges of DATACLK. See Figure 11.

Figure 11. Data Interface in Receive Mode

By being in control of bit timing, the MICRF507 is

effectively the “master.” For maximum timing margin, the

microcontroller, as the “slave,” can present or sample

(during transmit and receive, respectively) each new bit at

the DATAIXO pin at falling edges of DATACLK.

Additional Considerations in the Use of Synchronizer

(Sync_en = 1)

Two clock signals, BITRATE_CLK and BITSYNC_CLK,

must

properly

programmed

when

using

the

synchronizer. BITRATE_CLK, used in transmission, must

set

frequency

equal

the

bit

rate.

BITSYNC_CLK, used in reception, must have a frequency

16 times the bit rate. These frequencies are controlled by

the crystal oscillator frequency and the settings of register

fields, as described in the “Clock Generation” section. Bit

clocking of the incoming signal must agree with the

receiver’s local clocking within

±2.5% (easily met with 100

PPM or better crystals). For example, if fBITSYNC_CLK is

16x19.231kbps, the incoming bit rate can be between

0.975x19.231kbps to 1.025x19.231kbps.

All incoming messages must start with a 0101… preamble

so that the synchronizer can acquire the incoming clock. A

24-bit preamble is typically used; a minimum of 22 bits is

required.

MICRF507 Datasheet(PDF) 19 Page - Micrel Semiconductor

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