MICRF507 datasheet(23/47 Pages) MICREL

23 / 47 page

Micrel, Inc.

MICRF507

October 2, 2013

Revision 2.2

Figure 14. Second and Third Order Loop Filter

Table 12 shows three different loop filter designs, the first

two for VCO modulation and the last one for modulation

using the internal dividers. The component values are

calculated with RF frequency = 490MHz, VCO gain =

67MHz/V as seen by the PLL, and desired phase margin =

56º. Other settings are shown in the table. The VARIN pin

capacitance (pin 29) of 6pF can be neglected for the two

filters with lowest bandwidth (which have R2=0 and

relatively large values of C1). For other loop bandwidth

and phase detector values, use the loop filter calculation

tool in RF Testbench software available on Micrel’s

website.

Lock Detect

A lock detector can be enabled by setting LD_en = 1.

When pin LD is high, it indicates that the PLL is in lock.

After a control word is loaded LD will (typically) go low,

then high again when the synthesizer has locked. LD also

goes low initially when the PA (power amplifier) is turning

on.

After the transceiver has been put into Receive or

Transmit mode, or after the power amplifier has been

turned on, a low-to-high transition at LD can serve as an

indicator that the synthesizer frequency has stabilized.

Encoded

Bit Rate

(kbps)

PLL

(kHz)

Charge

Pump

(

μA)

Phase

Detector

Freq. (kHz)

VCO

0.8

125

100

10nF

100nF

6.2kΩ

VCO

>32

3.2

125

100

680pF

6.8nF

22kΩ

Divider

<6.5

500

390pF

8.2nF

5kΩ

68kΩ

18pF

Table 12. Loop Filter Component Values

MICRF507 Datasheet(PDF) 23 Page - Micrel Semiconductor

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