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MCP8026 Datasheet(PDF) 36 Page - Microchip Technology

Part # MCP8026
Description  3-Phase Brushless DC (BLDC) Motor Gate Driver with Power Module, Sleep Mode, and LIN Transceiver
PDF  64 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP8026 Datasheet(HTML) 36 Page - Microchip Technology

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MCP8025/6
DS20005339B-page 36
 2016 Microchip Technology Inc.
The FAULT/TXE pin will go low whenever the internal
circuits have detected a short circuit and have disabled
the LIN_BUS output driver. The MCP8025 limits the
transmitter current to less than 200 mA when a short
circuit is detected. If the host MCU is driving the
FAULT/TXE pin high, then the transmitter will remain
enabled and the fault condition will be overruled. If the
host MCU is driving the pin low or is in High Z mode,
the MCP8025 will drive the pin low and will disable the
LIN transmitter.
4.5.1.3
LIN Dominant State Timeout
The MCP8025 has an additional LIN feature, LIN
Dominant State Timeout, that is not in the current LIN
2.0 specification. If the LIN TX pin is externally held low
for more than the time specified by tDOM_TOUT, the
MCP8025 will disable the LIN transmitter. The
FAULT/TXE pin will go low, indicating a LIN Dominant
State Timeout fault. Forcing the FAULT/TXE pin high
will not re-enable the transmitter. The transmitter will
stay disabled until the TX pin is set high again. This
prevents the LIN transceiver from inadvertently locking
up the bus.
4.5.2
LEVEL TRANSLATOR (MCP8026)
The level translators are an interface between the
companion microcontroller’s logic levels and the input
voltage
levels
from
the
system.
Automotive
applications typically drive the inputs from the Engine
Control Unit (ECU) and the ignition key on/off signals.
The level translators are unidirectional translators.
Signals on the high-voltage input are translated to
low-voltage signals on the low-voltage outputs. The
high-voltage HV_IN[1:2] inputs have a configurable
30 k
 pull up. The pull up is configured via a
SET_CFG_0
message. The PU30K bit in the
CFG0 register controls the state of the pull up. The bit
may only be changed when the CE pin is low. The
low-voltage LV_OUT[1:2] outputs are open-drain
outputs. The outputs are capable of sinking a minimum
of 1 mA of current while maintaining less than 50 mV at
the output.
The HV_IN1 translator is also used to wake up the
device from the Sleep mode whenever the HV_IN1
input is transitioned to a low level for a minimum of
250 µs followed by a transition to the high voltage level.
TABLE 4-6:
FAULT/TXE TRUTH TABLE
TX
In
RX
Out
LIN_BUS
I/O
FAULT/TXE
Definition
External
Input
Driven
Output
LH
VDD
High Z
L
FAULT
, TX driven low, LIN_BUS shorted to VDD (Note 1)
LH
VDD
HL
FAULT
, Overridden by CPU driving FAULT/TXE high
HH
VDD
High Z, H
H
OK
HL
GND
High Z, H
H
OK
, data is being received from the LIN_Bus
LL
GND
High Z, H
H
OK
L
L
GND
V
DD
High Z, H
L
FAULT
, if TX is low longer than tDOM_TOUT
xx
VDD
Lx
NO FAULT
, the CPU is commanding the transceiver to
turn off the transmitter driver
Legend:
x = don’t care
Note 1:
The FAULT/TXE is valid approximately 25 µs after the TXD falling edge. This helps eliminate false fault
reporting during bus propagation delays.
Note:
The TQFP package has two level
translators. The second level translator
typically interfaces to an ignition key on/off
signal.



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