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MCP8026 Datasheet(PDF) 16 Page - Microchip Technology |
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MCP8026 Datasheet(HTML) 16 Page - Microchip Technology |
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16 / 64 page ![]() MCP8025/6 DS20005339B-page 16 2016 Microchip Technology Inc. TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges (Note 1) Specified Temperature Range TA -40 +150 °C Operating Temperature Range TA -40 +150 °C TJ -40 +160 °C Storage Temperature Range TA -55 +150 °C (Note 2) Package Thermal Resistances Thermal Resistance, 5 mm x 5 mm 40LD-QFN JA — 37 — °C/W 4-Layer JC51-5 standard board Natural convection JC —6.9 — Thermal Resistance, 7 mm x 7 mm 48LD-TQFP with Exposed Pad JA —30 — °C/W JC —15 — Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum 160°C rating. Sustained junction temperatures above 160°C can impact the device reliability. 2: 1000 hour cumulative maximum for ROM data retention (typical). ESD, SUSCEPTIBILITY, SURGE AND LATCH-UP TESTING Parameter Standard and Test Condition Value Input voltage surges ISO 16750-2 28V for 1 minute, 45V for 0.5 seconds ESD according to IBEE LIN EMC – Pins LIN_BUS, VDD (HMM) Test specification 1.0 following IEC 61000-4.2 ± 8 kV ESD HBM with 1.5 k /100 pF CEI/IEC 60749-26: 2006 AEC-Q100-002-Ref E JEDEC JS-001-2012 ±2 kV ESD HBM with 1.5 k /100 pF – Pins LIN_BUS, VDD, HV_IN1 against PGND CEI/IEC 60749-26: 2006 AEC-Q100-002-Ref E JEDEC JS-001-2012 ±8 kV ESD CDM (Charged Device Model, field-induced method – replaces machine-model method) ESD-STM5.3.1-1999 ± 750V all pins Latch-Up Susceptibility AEC Q100-004, 150°C > 100 mA |
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