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MCP8026 Datasheet(PDF) 38 Page - Microchip Technology

Part # MCP8026
Description  3-Phase Brushless DC (BLDC) Motor Gate Driver with Power Module, Sleep Mode, and LIN Transceiver
PDF  64 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP8026 Datasheet(HTML) 38 Page - Microchip Technology

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MCP8025/6
DS20005339B-page 38
 2016 Microchip Technology Inc.
FIGURE 4-4:
DE2 Packet Format.
FIGURE 4-5:
DE2 Packet Timing.
4.5.4
MESSAGING INTERFACE
A command byte will always have the most significant
bit 7 (MSb) set to ‘1’. Bits 6 and 5 are reserved for future
use and should be set to ‘0’. Bits 4–0 are used for
commands. That allows for 32 possible commands.
4.5.4.1
Host to MCP8025/6
Messages sent from the host to the MCP8025/6
devices consist of either one or two eight-bit bytes. The
first byte transmitted is the command byte. The second
byte transmitted, if required, is the data for the
command.
If a multi-byte command is sent to the MCP8025/6
devices and no second byte is received by the
MCP8025/6 devices, then a ‘Not Acknowledged’
(NACK) message will be sent back to the host after a
5 ms time-out period.
4.5.4.2
MCP8025/6 to Host
A solicited response byte from the MCP8025/6 devices
will always echo the command byte with bit 7 set to ‘0’
(Response) and with bit 6 set to ‘1’ for ‘Acknowledged’
(ACK) or ‘0’ for ‘Not Acknowledged’ (NACK). The
second byte, if required, will be the data for the host
command. Any command that causes an error or is not
supported will receive a NACK response.
The MCP8025/6 devices may send unsolicited
command messages to the host controller. No
message to the host controller requires a response
from the host controller.
STOP
START
DE2
Message Format
B0
B1
B2
B3
B4
B5
B6
B7
STOP
START
B0
B1
B2
B3
B4
B5
B6
B7
TSTART = 1.5T – uncertainty on start
Detection (worse case: 2x TS)
TS = T/16 (oversampled bit-cell period)
Receiver samples the incoming data
using x16 baud rate clock
Sample incoming data
at the bit-cell center
TS
TSTART
T
T = 1/Baud Rate (bit-cell period)
Detect start bit by sensing
transition from logic 1 to logic 0
worst



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