DS2155 datasheet(132/262 Pages) DALLAS

132 / 262 page

DS2156

132 of 262

22.

HDLC CONTROLLERS

This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is

configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each HDLC

controller has 128-byte buffers in the transmit and receive paths. When used with time slots, the user can

select any time slot or multiple time slots, contiguous or noncontiguous, as well as any specific bits

within the time slot(s) to assign to the HDLC controllers.

The user must not map both transmit HDLC controllers to the same Sa bits, time slots or, in T1 mode,

map both controllers to the FDL. HDLC #1 and HDLC #2 are identical in operation and therefore the

following operational description refers only to a singular controller.

The HDLC controller performs the entire necessary overhead for generating and receiving performance

report messages (PRMs) as described in ANSI T1.403 and the messages as described in AT&T TR54016.

The HDLC controller automatically generates and detects flags, generates and checks the CRC check

sum, generates and detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream.

The 128-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or

transmitted without host intervention.

22.1 Basic Operation Details

The HDLC registers are divided into four groups: control/configuration, status/information, mapping, and

FIFOs. Table 22-A lists these registers by group.

22.2 HDLC Configuration

The HxTC and HxRC registers perform the basic configuration of the HDLC controllers. Operating

features such as CRC generation, zero stuffer, transmit and receive HDLC mapping options, and idle

flags are selected here. These registers also reset the HDLC controllers.

DS2155 Datasheet(PDF) 132 Page - Dallas Semiconductor