DS2155 datasheet(148/262 Pages) DALLAS

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DS2156

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22.5.3

Transmit Section

The transmit section shifts out into the T1 data stream either the FDL (in the ESF framing mode) or the

Fs bits (in the D4 framing mode) contained in the transmit FDL register (TFDL). When a new value is

written to the TFDL, it is multiplexed serially (LSB first) into the proper position in the outgoing T1 data

stream. After the full 8 bits have been shifted out, the framer signals the host microcontroller by setting

the SR8.2 bit to a 1 that the buffer is empty and that more data is needed. The INT also toggles low if

enabled through IMR8.2. The user has 2ms to update the TFDL with a new value. If the TFDL is not

updated, the old value in the TFDL is transmitted once again. The framer also contains a zero stuffer that

is controlled through the T1TCR2.5 bit. In both ANSI T1.403 and TR54016, communications on the FDL

follows a subset of an LAPD protocol. The LAPD protocol states that no more than five 1s should be

transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort

signal (11111111). If enabled through T1TCR2.5, the framer automatically looks for five 1s in a row. If it

finds such a pattern, it automatically inserts a 0 after the five 1s. The T1TCR2.5 bit should always be set

to a 1 when the framer is inserting the FDL.

TFDL

Transmit FDL Register

C1h

Bit #

Name

TFDL7

TFDL6

TFDL5

TFDL4

TFDL3

TFDL2

TFDL1

TFDL0

Default

Note: Also used to insert Fs framing pattern in D4 framing mode.

The transmit FDL register (TFDL) contains the FDL information that is to be inserted on a byte basis into the

outgoing T1 data stream. The LSB is transmitted first.

Bit 0/Transmit FDL Bit 0 (TFDL0). LSB of the transmit FDL code.

Bit 1/Transmit FDL Bit 1 (TFDL1)

Bit 2/Transmit FDL Bit 2 (TFDL2)

Bit 3/Transmit FDL Bit 3 (TFDL3)

Bit 4/Transmit FDL Bit 4 (TFDL4)

Bit 5/Transmit FDL Bit 5 (TFDL5)

Bit 6/Transmit FDL Bit 6 (TFDL6)

Bit 7/Transmit FDL Bit 7 (TFDL7). MSB of the transmit FDL code.

22.6 D4/SLC-96 Operation

In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the

device to properly insert the Fs framing pattern, the TFDL register at address C1h must be programmed to

1Ch and the following bits must be programmed as shown:

T1TCR1.2 = 0 (source Fs data from the TFDL register)

T1TCR2.6 = 1 (allow the TFDL register to load on multiframe boundaries)

Since the SLC-96 message fields share the Fs-bit position, the user can access these message fields

through the TFDL and RFDL registers. Refer to Application Note 345: DS2141A, DS2151, DS2152 SLC-

96 for a detailed description about implementing an SLC-96 function.

DS2155 Datasheet(PDF) 148 Page - Dallas Semiconductor

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