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70T653MS12BCGI Datasheet(PDF) 16 Page - Integrated Device Technology

Part # 70T653MS12BCGI
Description  HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
PDF  24 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

70T653MS12BCGI Datasheet(HTML) 16 Page - Integrated Device Technology

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IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
16
Timing Waveform of Write with BUSY
NOTES:
1. tWH must be met for BUSY input.
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
5679 drw 15
R/
W"A"
BUSY"B"
tWB
R/
W"B"
tWH
(1)
(2)
tWP
.
5679 drw 14a
tDW
ADDR"A"
tWC
DATAOUT "B"
MATCH
tWP
R/
W"A"
DATAIN "A"
ADDR"B"
tDH
VALID
MATCH
R/
W"B"
VALID
tDDD
(3)
tWDD
.
(4)
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
70T653MS10
Com'l Only
70T653MS12
Com'l
& Ind
70T653MS15
Com'l Only
Symbol
Parameter
Min.Max.Min.Max.Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tINS
Interrupt Set Time
____
10
____
12
____
15
ns
tINR
Interrupt Reset Time
____
10
____
12
____
15
ns
5679 tbl 16
NOTES:
1. Timing is the same for both ports.
2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
Timing Waveform of Write with Port-to-Port Read(1,3)
NOTES:
1. CE0L = CE0R = VIL; CE1L = CE1R = VIH.
2. OE = VIL for the reading port.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
4. R/WB = VIH.



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