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70T653MS12BCGI Datasheet(PDF) 18 Page - Integrated Device Technology

Part # 70T653MS12BCGI
Description  HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
PDF  24 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

70T653MS12BCGI Datasheet(HTML) 18 Page - Integrated Device Technology

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IDT70T653M
High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
18
semaphore flags. These flags allow either processor on the left or
right side of the Dual-Port RAM to claim a privilege over the other
processorforfunctionsdefinedbythesystemdesigner’ssoftware.As
an example, the semaphore can be used by one processor to inhibit
the other from accessing a portion of the Dual-Port RAM or any other
shared resource.
TheDual-PortRAMfeaturesafastaccesstime,withbothportsbeing
completelyindependentofeachother.Thismeansthatthe activityonthe
left port in no way slows the access time of the right port. Both ports are
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom
orwrittentoatthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledby CE0andCE1,theDual-
PortRAMchipenables,andSEM,thesemaphoreenable.TheCE0,CE1,
and SEM pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
Systems which can best use the IDT70T653M contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These ystems can
benefit from a performance increase offered by the IDT70T653Ms
hardware semaphores, which provide a lockout mechanism without
requiringcomplexprogramming.
Software handshaking between processors offers the maximum in
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations. The IDT70T653M does not use its semaphore flags to
control any resources through hardware, thus allowing the system
designertotalflexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
Functional Description
TheIDT70T653Mprovidestwoportswithseparatecontrol,address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70T653M has an automatic power down
feature controlled by CE. The CE0 and CE1 control the on-chip power
downcircuitrythatpermitstherespectiveporttogointoastandbymode
when not selected (CE = HIGH). When a port is enabled, access to the
entirememoryarrayispermitted.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FFFE
(HEX),whereawriteisdefinedasCER=R/WR=VILpertheTruthTable.
Theleftportclearstheinterruptthroughaccessofaddresslocation7FFFE
when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port
interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation
7FFFF(HEX)andtocleartheinterruptflag(INTR),therightportmustread
thememorylocation7FFFF.Themessage(36bits)at7FFFEor7FFFF
isuser-definedsinceitisanaddressableSRAMlocation.Iftheinterrupt
function is not used, address locations 7FFFE and 7FFFF are not used
asmailboxes,butaspartoftherandomaccessmemory.RefertoTruth
Table III for the interrupt operation.
Busy Logic
TheBUSYpinoperatesasawriteinhibitinputpin.Normaloperation
canbeprogrammedbytyingtheBUSYpinsHIGH.Ifdesired,unintended
writeoperationscanbepreventedtoaportbytyingtheBUSYpinforthat
port LOW.
Semaphores
The IDT70T653M is an extremely fast Dual-Port 512K x 36 CMOS
StaticRAMwithanadditional8addresslocationsdedicatedtobinary
Truth Table IV — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T653M.
2. There are eight semaphore flags written to via I/O0 and read from I/Os (I/O0-I/O8 and I/O18-I/O26). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functions
D0 - D8 Left
D18 - D26 Left
D0 - D8 Right
D18 - D26 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
5679 tbl 19



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