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70T653MS12BCGI Datasheet(PDF) 1 Page - Integrated Device Technology |
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70T653MS12BCGI Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 24 page  ©2015 Integrated Device Technology, Inc. 1 JUNE 2015 DSC-5679/6 CE0R R/ WR CE1R BE0R BE1R BE2R BE3R 512K x 36 MEMORY ARRAY Address Decoder A18R A0R Address Decoder CE0L R/ WL CE1L BE0L BE1L BE2L BE3L Dout0-8_L Dout9-17_L Dout18-26_L Dout27-35_L Dout0-8_R Dout9-17_R Dout18-26_R Dout27-35_R B E 0 L B E 1 L B E 2 L B E 3 L B E 3 R B E 2 R B E 1 R B E 0 R I/O0L- I/O35L A18L A0L I/O0R -I/O35R Di n_L ADDR_L Di n_R ADDR_R OER OEL ARBITRATION INTERRUPT SEMAPHORE LOGIC SEML INTL(1) BUSYL R/ WL OEL R/ WR OER CE0L CE1L CE0R CE1R BUSYR SEMR INTR(1) 5679 drw 01 ZZ CONTROL LOGIC ZZL(2) JTAG TCK TRST TMS TDI TDO ZZR(2) Functional Block Diagram ◆ ◆ ◆ ◆ ◆ Full on-chip hardware support of semaphore signaling between ports ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port ◆ Separate byte controls for multiplexed bus and bus matching compatibility ◆ ◆ ◆ ◆ ◆ Sleep Mode Inputs on both ports ◆ ◆ ◆ ◆ ◆ Single 2.5V (±100mV) power supply for core ◆ ◆ ◆ ◆ ◆ LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port ◆ ◆ ◆ ◆ ◆ Includes JTAG functionality ◆ ◆ ◆ ◆ ◆ Available in a 256-ball Ball Grid Array ◆ ◆ ◆ ◆ ◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆ ◆ ◆ ◆ ◆ Green parts available, see ordering information Features ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial: 10/12/15ns (max.) – Industrial: 12ns (max.) ◆ ◆ ◆ ◆ ◆ RapidWrite Mode simplifies high-speed consecutive write cycles ◆ ◆ ◆ ◆ ◆ Dual chip enables allow for depth expansion without external logic ◆ ◆ ◆ ◆ ◆ IDT70T653M easily expands data bus width to 72 bits or more using the Busy Input when cascading more than one device ◆ ◆ ◆ ◆ ◆ Busy input for port contention management ◆ ◆ ◆ ◆ ◆ Interrupt Flags HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE IDT70T653M NOTES: 1. INT is non-tri-state totem-pole outputs (push-pull). 2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. |
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