70T653MS12BCGI datasheet(11/24 Pages) IDT

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IDT70T653M

High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)

Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5,8)

NOTES:

1. R/W or CE or BEn = VIH during all address transitions for Write Cycles 1 and 2.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle.

3. tWR is measured from the earlier of CE, BEn or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 1).

8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL

and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.

tWC

tHZ

tAW

tWR

tAS

tWP

DATAOUT

(2)

tWZ

tDW

tDH

tOW

ADDRESS

DATAIN

CE or SEM

(9)

(6)

(4)

(3)

5679 drw 10

(7)

tLZ

tHZ

(7)

BEn

(9)

5679 drw 11

tWC

tAS

tWR

tDW

tDH

ADDRESS

DATAIN

tAW

tEW

BEn

(3)

(2)

(6)

CE or SEM

(9)

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