34C60 datasheet(24/58 Pages) SMSC

24 / 58 page

SMSC DS – PPC34C60

Page 24

Rev. 06/01/2001

ADVANCED INFORMATION

OPERATION REGISTER - 0100 (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCLR

INTEN

AUTO-INC

PDMA

DIREC

DMAEN

D16

F16

The bits in this register control the operation of the PPC34C60.

Bit 0:F16

Setting this bit overrides Pin 81 (nIO16), forcing all bus accesses to 16-bit. Use this bit to access a 16-bit peripheral which

does not generate nIO16.

Bit 1:D16

This bit controls the bus width of the DMA cycles. 1 selects 16-bit, 0 selects 8-bit. nIO16 and F16 are ignored during DMA

cycles.

Bit 2:DMAEN

This bit must be set for the DMA state machine to recognize DREQs. This bit will be automatically cleared when the DMA

is complete.

Bit 3:DIREC

This bit controls the direction of DRAM - BUS DMA cycles. 1 selects a write from DRAM to BUS, 0 selects a read from

BUS to DRAM.

Bit 4:PDMA

Setting this bit enables the psuedo-DMA mode. In the PDMA mode DMA functions are performed, but CS is used instead

of DACK to qualify the bus cycles. Use the PDMA mode to DMA to or from a device which does not explicitly support DMA.

Bit 5:AUTOINC

Setting this bit causes the bus address (A0-A7) to increment after every bus access.

Bit 6:INTEN

Setting this bit enables the interrupt latch.

Bit 7:INTCLR

Writing a 1 to this bit will clear any pending interrupt. This bit always reads 0.

DRAM BUFFER SIZE REGISTER - 0101 (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DMA DRAM BUFFER SIZE

HOST DRAM BUFFER SIZE

This register determines the size of the DRAM buffers, both for DMA DRAM and Host DRAM accesses. The buffer sizes

are encoded as follows:

0001

Bytes

1001

512

Bytes

0010

Bytes

1010

1 K

Bytes

0011

Bytes

1011

2 K

Bytes

0100

Bytes

1100

4 K

Bytes

0101

Bytes

1101

8 K

Bytes

0110

Bytes

1110

16 K

Bytes

0111

128

Bytes

1111

32 K

Bytes

1000

256

Bytes

0000

64 K

Bytes

34C60 Datasheet(PDF) 24 Page - SMSC Corporation

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