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34C60 Datasheet(PDF) 49 Page - SMSC Corporation

Part # 34C60
Description  PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE
PDF  58 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

34C60 Datasheet(HTML) 49 Page - SMSC Corporation

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SMSC DS – PPC34C60
Page 49
Rev. 06/01/2001
ADVANCED INFORMATION
FIGURE 20 - ECP REVERSE DATA TRANSFER TIMING
(ECP DATA READ, PARALLEL PORT SIGNALS)
Note: The optional use of the nERR (nFAULT) line to "hint" to the Host that the peripheral has data to send to the Host is
not supported in the PPC34C60. The driver should ignore any activity on this line. The PPC34C60 supports reverse data
transfers only (not reverse command transfers) and, therefore, always asserts the BSY (nCMD) signal during reverse
transfers.
See ECP Reverse Data Transfer Timing Parameters.
ECP REVERSE DATA TRANSFER TIMING (ECP DATA READ, PARALLEL PORT SIGNALS)
PARAMETER
MIN
TYP
MAX
UNITS
t1
To prepare for an ECP reverse channel transfer the Host tri-
states the parallel data lines HD[0:7] and asserts nALF at the
same time. Next the Host asserts nINIT to initiate an ECP bus
reversal. The PPC34C60 requires this amout of time between
these events.
0
ns
t2
The PPC34C60 acknowledges the bus reversal by
deasserting the PE signal. At this point in time the parallel port
bus is in the reverse idle state.
208
[5 SCLK]
334
[8 SCLK]
ns
t3
Along with deasserting the PE signal the PPC34C60 takes
control of the parallel port data bus HD[0:7]. The data on this
bus remains undefined until the PPC34C60 has accessed and
placed a data byte on the bus. Along with driving the data lines
with valid data, the PPC34C60 asserts BSY to indicate that
this is a data transfer.
0
1,084
[13
BCLK]
ns
t4
After placing data on the parallel port data lines the
PPC34C60 asserts nACK to inform the Host that valid data is
available.
125
[3 SCLK]
167
[4 SCLK]
ns
t5
Next, the Host will acknowledge that it is ready for the data by
deasserting nALF.
50
infinite
ns
t6
Now the PPC34C60 will deassert nACK in response to the
Host. The Host will latch the data on HD[0:7] on this rising
edge of nACK.
125
[3 SCLK]
167
[4 SCLK]
ns
t7
The Host completes the ECP reverse transfer, acknowledging
that it has accepted the data byte by asserting nALF.
50ns
1s
VALID DATA
t3
t8
t9
t11
t5
t7
t1
t4
t6
t2
t10
HD[0:7]
nSTB H
nALF H
nSEL H
nINIT H
BSY P
nACK P
PE P
SLCT P
nERR P
DATA



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