DS2196 datasheet(108/157 Pages) DALLAS

108 / 157 page

DS2196

108 of 157

RHIRA: RECEIVE HDLC INFORMATION REGISTER FRAMER A

(Address = 03 Hex)

RHIRB: RECEIVE HDLC INFORMATION REGISTER FRAMER B

(Address = A3 Hex)

(MSB)

(LSB)

RABT

RCRCE

ROVR

RVM

REMPTY

POK

CBYTE

OBYTE

SYMBOL

POSITION

NAME AND DESCRIPTION

RABT

RHIR.7

Abort Sequence Detected. Set whenever the HDLC

controller sees 7 or more 1’s in a row.

RCRCE

RHIR.6

CRC Error. Set when the CRC checksum is in error.

ROVR

RHIR.5

Overrun. Set when the HDLC controller has attempted to

write a byte into an already full receive FIFO.

RVM

RHIR.4

Valid Message. Set when the HDLC controller has detected

and checked a complete HDLC packet.

REMPTY

RHIR.3

Empty. A real–time bit that is set high when the receive FIFO

is empty.

POK

RHIR.2

Packet OK. Set when the byte available for reading in the

receive FIFO at RHFR is the last byte of a valid message (and

hence no abort was seen, no overrun occurred, and the CRC

was correct).

CBYTE

RHIR.1

Closing Byte. Set when the byte available for reading in the

receive FIFO at RHFR is the last byte of a message (whether

the message was valid or not).

OBYTE

RHIR.0

Opening Byte. Set when the byte available for reading in the

receive FIFO at RHFR is the first byte of a message.

NOTE:

The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.

DS2196 Datasheet(PDF) 108 Page - Dallas Semiconductor

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