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DM505 Datasheet(PDF) 176 Page - Texas Instruments |
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DM505 Datasheet(HTML) 176 Page - Texas Instruments |
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176 / 290 page  SPRS916_Intro_001 JTAG PLLs OSC Memory Controllers GPMC 8b/16b with up to 16b ECC LPDDR2 / DDR2/ DDR3 / DDR3L 32b with 8b ECC Timer x8 Mailbox/Spinlock 10-bit ADC Control Module EDMA GPIO x4 PWMSSx1 MMUx1 PRCM System I2C x2 SPI x4 QSPI x1 SDIO x1 DCAN with ECC UART x3 McASP x3 Serial Interfaces GMAC Connectivity EDMA 2TC L2 256KB Cache C66x L1D 32KB L1P 32KB DSP Subsystem x2 Video Input Port CAL LVDSRX CSI2 ISP Video Front End up to 512KB RAM with ECC IPU with ECC Dual Cortex M4 32KB ROM EVE 16MAC EDMA 2TC Vision Accelerator OSD Resizing CSC SD-DAC DVOUT Display Subsystem Interconnect DM505 Copyright © 2016, Texas Instruments Incorporated MCAN(CAN-FD) with ECC 176 DM505 SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 www.ti.com Submit Documentation Feedback Detailed Description Copyright © 2016–2017, Texas Instruments Incorporated Figure 6-1. DM505 Block Diagram 6.3 DSP Subsystem The device includes two identical instances (DSP1 and DSP2) of a digital signal processor (DSP) subsystem, based on the TI's standard TMS320C66x™ DSP CorePac core. The TMS320C66x DSP core enhances the TMS320C674x™ core, which merges the C674x™ floating point and the C64x+™ fixed-point instruction set architectures. The C66x DSP is object-code compatible with the C64x+/C674x DSPs. For more information on the TMS320C66x core CPU, see the TMS320C66x DSP CPU and Instruction Set Reference Guide, (SPRUGH7). Each of the two DSP subsystems integrated in the device includes the following components: |
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