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DM505 Datasheet(PDF) 172 Page - Texas Instruments |
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DM505 Datasheet(HTML) 172 Page - Texas Instruments |
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172 / 290 page  172 DM505 SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 www.ti.com Submit Documentation Feedback Specifications Copyright © 2016–2017, Texas Instruments Incorporated Table 5-77. GPIO2/3/4 IOSETs (continued) SIGNALS IOSET1 IOSET2 BALL MUX BALL MUX GPIO3 gpio3_0 AB15 14 gpio3_9 U9 14 U9 14 gpio3_10 W11 14 W11 14 gpio3_11 V9 14 V9 14 gpio3_12 W9 14 W9 14 gpio3_13 U8 14 U8 14 gpio3_14 W8 14 W8 14 gpio3_15 U7 14 gpio3_16 V7 14 GPIO4 gpio4_4 R5 14 gpio4_6 N4 14 gpio4_7 R7 14 gpio4_8 L2 14 gpio4_9 N5 14 gpio4_10 N6 14 5.9.7 Emulation and Debug Subsystem The device includes the following Test interfaces: • IEEE 1149.1 Standard-Test-Access Port (JTAG) • Trace Port Interface Unit (TPIU) 5.9.7.1 JTAG Electrical Data/Timing Table 5-78, Table 5-79 and Figure 5-57 assume testing over the recommended operating conditions and electrical characteristic conditions below. Table 5-78. Timing Requirements for IEEE 1149.1 JTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT 1 tc(TCK) Cycle time, TCK 62.29 ns 1a tw(TCKH) Pulse duration, TCK high (40% of tc) 24.92 ns 1b tw(TCKL) Pulse duration, TCK low(40% of tc) 24.92 ns 3 tsu(TDI-TCK) Input setup time, TDI valid to TCK high 6.23 ns tsu(TMS-TCK) Input setup time, TMS valid to TCK high 6.23 ns 4 th(TCK-TDI) Input hold time, TDI valid from TCK high 31.15 ns th(TCK-TMS) Input hold time, TMS valid from TCK high 31.15 ns Table 5-79. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG NO. PARAMETER DESCRIPTION MIN MAX UNIT 2 td(TCKL-TDOV) Delay time, TCK low to TDO valid 0 30.5 ns |
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