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DM505 Datasheet(PDF) 199 Page - Texas Instruments |
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DM505 Datasheet(HTML) 199 Page - Texas Instruments |
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199 / 290 page  199 DM505 www.ti.com SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 Submit Documentation Feedback Detailed Description Copyright © 2016–2017, Texas Instruments Incorporated • Flow Control Support (802.3x) • Digital loopback and FIFO loopback modes supported • Maximum frame size 2016 bytes (2020 with VLAN) • 8k (2048 × 32) internal CPPI buffer descriptor memory • Management Data Input/Output (MDIO) module for PHY Management • Programmable interrupt control with selected interrupt pacing • Emulation support • Programmable Transmit Inter Packet Gap (IPG) • Reset isolation (switch function remains active even in case of all device resets except for POR pin reset and ICEPICK cold reset) • Full duplex mode supported in 10/100/1000 Mbps. Half-duplex mode supported only in 10/100 Mbps. • IEEE 802.3 gigabit Ethernet conformant For more information, see section Gigabit Ethernet Switch (GMAC_SW) in chapter Serial Communication Interfaces of the device TRM. 6.10.14 SDIO The SDIO host controller provides an interface between a local host (LH) such as a microprocessor unit or digital signal processor and SDIO cards. It handles SDIO transactions with minimal LH intervention. The SDIO host controller deals with SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit, and checking for syntactical correctness. The application interface can send every SDIO command and poll for the status of the adapter or wait for an interrupt request, which is sent back in case of exceptions or to warn of end of operation. The application interface can read card responses or flag registers. It can also mask individual interrupt sources. All these operations can be performed by reading and writing control registers. The SDIO host controller also supports two slave DMA channels. Compliance with standards: • SDIO command/response sets and interrupt/read-wait suspend-resume operations as defined in the SD part E1 specification v3.00 • SD command/response sets as defined in the SD Physical Layer specification v3.01 • SD Host Controller Standard Specification sets as defined in the SD card specification Part A2 v3.00 Main features of the SD/SDIO host controllers: • Flexible architecture allowing support for new command structure • 32-bit wide access bus to maximize bus throughput • Designed for low power • Programmable clock generation • L4 slave interface supports: – 32-bit data bus width – 8/16/32 bit access supported – 9-bit address bus width – Streaming burst supported only with burst length up to 7 – WNP supported • Built-in 1024-byte buffer for read or write • Two DMA channels, one interrupt line • Supported data transfer rates up to SDR25 mode • The SDIO controller is connected to 1,8V/3.3V compatible I/Os to support 1,8V/3.3V signaling |
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