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DM505 Datasheet(PDF) 215 Page - Texas Instruments |
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DM505 Datasheet(HTML) 215 Page - Texas Instruments |
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215 / 290 page  Minimize such inductance by optimizing layout Keep distance between protected circuit and external protection Keep protection closed by connector external External protection Stub inductance Ground inductance Signal ESD strike VCC Stub inductance Stub inductance Bypass capacitor 0.1 f (minimum) m Interconnection inductance vcc VCC Signal Protected circuit SPRS91v_PCB_ESD_01 215 DM505 www.ti.com SPRS976D – NOVEMBER 2016 – REVISED JULY 2017 Submit Documentation Feedback Applications, Implementation, and Layout Copyright © 2016–2017, Texas Instruments Incorporated Figure 7-10. Placement Recommendation for an ESD External Protection NOTE To ensure normal behavior of the ESD protection (unwanted leakage), it is better to ground the ESD protection to the board ground rather than any local ground (example isolated shield or audio ground). 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity • Avoid running critical signal traces (clocks, resets, interrupts, control signals, and so forth) near PCB edges. • Add high frequency filtering: Decoupling capacitors close to the receivers rather than close to the drivers to minimize ESD coupling. • Put a ground (guard) ring around the entire periphery of the PCB to act as a lightning rod. • Connect the guard ring to the PCB ground plane to provide a low impedance path for ESD-coupled current on the ring. • Fill unused portions of the PCB with ground plane. • Minimize circuit loops between power and ground by using multilayer PCB with dedicated power and ground planes. • Shield long line length (strip lines) to minimize radiated ESD. • Avoid running traces over split ground planes. It is better to use a bridge connecting the two planes in one area. |
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