S8340 datasheet(23/55 Pages) SII

23 / 55 page

STEP-UP, 600 kHz, PWM CONTROL OR PWM/PFM SWITCHABLE SWITCHING REGULATOR CONTROLLER

Rev.4.0_01

S-8340/8341 Series

5. External Transistors

Enhancement (N-channel) MOS FET type or bipolar (NPN) type can be used for the external transistors.

5. 1 Enhancement (N-Channel) MOS FET Type

The EXT pin can directly drive an N-channel MOS FET. When an N-channel MOS FET is used, efficiency will be 2

to 3% higher than that achieved by an NPN bipolar transistor since the MOS FET switching speed is faster and

power dissipation due to the base current is avoided.

A large current may flow at power on with some MOS FETs selected. Perform thorough evaluation using the

actual devices to select. The recommended gate capacitance of the MOS FET to be used is 1200 pF or smaller.

The important parameters in selecting a MOS FET are threshold voltage, breakdown voltage between drain and

source, total gate capacitance, on-resistance, and the current rating.

The EXT pin voltage swings between VDD and VSS. If VDD is low, a MOS FET of which the threshold voltage is low

enough so that the MOS FET is completely turned on must be used. If VDD is high, the breakdown voltage

between the gate and source must be higher by at least several volts.

During the step-up operation, voltage VOUT + VF is applied between the drain and source of the MOS FET. So the

breakdown voltage between the drain and source should be higher than the VOUT + VF voltage by at least several

volts.

The total gate capacitance and the on-resistance affect the efficiency.

The larger the total gate capacitance becomes and the higher the input voltage becomes, the more the power

dissipation for charging and discharging the gate capacitance by switching operation increases, and affects the

efficiency at low load current region. If the efficiency at low load is important, select MOS FETs with a small total

gate capacitance.

In the regions where the load current is high, the efficiency is affected by power dissipation caused by the

resistance of the MOS FETs. If the efficiency under heavy load is particularly important in the application, choose

MOS FETs which have an on-resistance as low as possible. As for the current rating, select a MOS FET whose

maximum continuous drain current rating is higher than IPK.

5. 2 Bipolar (NPN) Type

Figures 16 and 17 in “ Standard Circuits (2) Using Bipolar Transistors” show sample circuit diagrams using

Sanyo Electric Co., Ltd. 2SD1628G for the bipolar transistor (NPN). The driveability for increasing the output

current by means of a bipolar transistor depend on the hFE and Rb values of that bipolar transistor.

The Rb value is given by the following equation :

Rb=

−

Find the necessary base current (Ib) using the hFE value of the bipolar transistor by the equation, Ib

= IPK/hFE, and

select a smaller Rb value.

A small Rb value can increase the output current, but the efficiency decreases. A current may flow as the pulses or

voltage drops take place due to the wiring resistance or some other reason. Determine an optimum value through

experimentation.

In addition, if a speed-up capacitor (Cb) is inserted in parallel with the resistance (Rb) as shown in Figures 16 and

17, the switching loss will be reduced, leading to a higher efficiency.

Select a Cb value by using the following equation as a guide :

≤

fosc 0.1

π×

However, the optimum Cb value differs depending upon the characteristics of the bipolar transistor. Select a Cb

value after performing a thorough evaluation.

VDD

− 0.7

0.4

IEXTH

S8340 Datasheet(PDF) 23 Page - Seiko Instruments Inc

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