AD7770 datasheet(44/98 Pages) AD

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Data Sheet

AD7770

Rev. C | Page 43 of 97

Power Modes

The AD7770 offers different power modes to improve the power

efficiency, high resolution and low power mode, which can be

controlled via GENERAL_USER_CONFIG_1, Bit 6. To further

reduce the power, additional blocks can be disabled independently,

as described in Table 21.

If the power mode changes, a pulse on the SYNC_IN pin is

required.

LDO Bypassing

The internal LDOs can be individually bypassed and an external

supply can be applied directly to the AREG1CAP, AREG2CAP,

or DREGCAP pin. Table 22 shows the absolute minimum and

maximum supplies for these pins, as well as the associated

Table 22. LDO Bypassing

LDO

BUFFER_CONFIG_2,

Bits[2:0]1

Supply

Max (V)

Min (V)

AREG1CAP

1XX

1.9

1.85

AREG2CAP

X1X

1.9

1.85

DREGCAP

XX1

1.98

1.65

X means don’t care.

DIGITAL SPI

The SPI serial interface on the AD7770 consists of four

signals: CS, SDI, SCLK, and SDO. A typical connection diagram

of the SPI is shown in Figure 101.

DSP/FPGA

AD7770

SCLK

SDI

SDO

Figure 101. SPI Control Interface—AD7770 is the SPI Slave, Digital Signal

Processor (DSP)/Field Programmable Gate Array (FPGA) is the Master

The SPI operates in Mode 0 and Mode 3: CPOL = 0, CPHA = 0

(Mode 0) or CPOL = 1, CPHA = 1 (Mode 3).

In pin control mode, the SDO can read back the Σ-Δ results,

depending on the level of the CONVST_SAR pin, as described in

Table 13.

In SPI control mode, the SPI transfers data into the on-chip

registers while the SDO pin reads back data from the on-chip

registers or reads the SAR or the Σ-Δ conversions results,

depending on the selected operation mode.

The SDO data source in SPI control mode is defined by the

GENERAL_USER_CONFIG_2 and GENERAL_USER_

CONFIG_3 registers, as described in Table 23.

Table 23. SPI Operation Mode in SPI Control Mode

GENERAL_USER_

CONFIG_2, Bit 5

Setting

GENERAL_USER_

CONFIG_3, Bit 4

Setting1

Mode

Internal register

Σ-Δ data conversion

SAR conversion

X means don’t care.

In SPI control mode, there are four different levels of I/O strength

on the SDO pin that can be selected in GENERAL_USER_

CONFIG_2, Bits[4:3], as described in Table 24.

Table 24. SDO Strength

GENERAL_USER_CONFIG_2, Bits[4:3] Setting

Mode

Nominal

Strong

Weak

Extra strong

SCLK is the serial clock input for the device. All data transfers

(on either SDO or SDI) occur with respect to this SCLK signal.

The SPI can operate in multiples of eight bits. For example, in

SPI control mode, if the SDO pin is used to read back the data

from the internal register or the SAR ADC, the data frame is 16 bits

wide (CRC disabled), as shown in Figure 102, or 24 bits wide (CRC

enabled), as shown in Figure 103. In this case, the controller can

generate one frame of 16 bits or 24 bits (with and without the

CRC enabled), or 2 or 3 frames of 8 bits (with and without the

CRC enabled). When the SDO pin reads back the data from the

Σ-Δ channels, 64 bits must be read back from the controller (in

this case, the controller can generate a frame of 64 bits—either

2 × 32 bits, 4 × 16 bits, or 8 × 8 bits).

SPI CRC—Checksum Protection (SPI Control Mode)

The AD7770 has a checksum mode that improves SPI

robustness in SPI control mode. Using the checksum ensures

that only valid data is written to a register and allows data read

from the device to be validated. The SPI CRC can be enabled by

setting the SPI_CRC_TEST_EN bit. If an error occurs during a

Enabling the SPI_CRC_TEST_EN bit results in a CRC checksum

being performed on all the R/W operations. When SPI_

CRC_TEST_EN is enabled, an 8-bit CRC word is appended

to every SPI transaction for SAR and register map operations.

For more information on Σ-Δ readback operations, see the

CRC Header section.

To ensure that the register write is successful, it is recommended to

read back the register and verify the checksum.

For CRC checksum calculations, the following polynomial is

always used: x8 + x2 + x + 1. See the SPI Control Mode

Checksum section for more information.

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