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AD7770 Datasheet(PDF) 71 Page - Analog Devices |
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AD7770 Datasheet(HTML) 71 Page - Analog Devices |
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71 / 98 page ![]() AD7770 Data Sheet Rev. C | Page 70 of 97 GENERAL USER CONFIGURATION 1 REGISTER Address: 0x011, Reset: 0x24, Name: GENERAL_USER_CONFIG_1 If all SD channels are disabled, setting this bit high allows DCLK to continue toggling Soft Reset 11: 1st write. 10: 2nd write. 01: No Effect. 00: No Effect. Power Mode 1: High Resolution. 0: Low Power (1/4) PowerDown signal for internal oscillator. Active Low PowerDown VCM Buffer. Active Low PowerDown SA. Active Low PowerDown Internal Reference Output Buffer. Active Low 0 0 1 0 2 1 3 0 4 0 5 1 6 0 7 0 [7] ALL_CH_DIS__MCLK_EN (R/W) [1:0] SOFT_RESET (R/W) [6] POWERMODE (R/W) [2] PDB_RC_OSC (R/W) [5] PDB_VCM (R/W) [3] PDB_SAR (R/W) [4] PDB_REFOUT_BUF (R/W) Table 62. Bit Descriptions for GENERAL_USER_CONFIG_1 Bits Bit Name Settings Description Reset Access 7 ALL_CH_DIS_MCLK_EN If all Σ-Δ channels are disabled, setting this bit high allows DCLK to continue toggling. 0x0 R/W 6 POWERMODE Power Mode. 0x0 R/W 0 Low power (1/4). 1 High resolution. 5 PDB_VCM Power Down VCM Buffer. Active low. 0x1 R/W 4 PDB_REFOUT_BUF Power Down Internal Reference Output Buffer. Active low. 0x0 R/W 3 PDB_SAR Power Down SAR. Active low. 0x0 R/W 2 PDB_RC_OSC Power Down Signal for Internal Oscillator. Active low. 0x1 R/W [1:0] SOFT_RESET Soft Reset. 0x0 R/W 00 No effect. 01 No effect. 10 2nd write. 11 1st write. GENERAL USER CONFIGURATION 2 REGISTER Address: 0x012, Reset: 0x09, Name: GENERAL_USER_CONFIG_2 SYNC pulse generated thru SPI 1: STARTb pin in the control module. This bit is ANDed with the value on 0: generate a pulse in /SYNC_IN pin. on STARTb pin in the control module, This signal is ANDed with the value DOUT Drive Strength 11: Extra Strong. 10: Weak. 01: Strong. 00: Nominal. Sets SPI interface to read back SAR result on SDO SDO Drive Strength 11: Extra Strong. 10: Weak. 01: Strong. 00: Nominal. 0 1 1 0 2 0 3 1 4 0 5 0 6 0 7 0 [7] RESERVED [0] SPI_SYNC (R/W) [6] RESERVED [2:1] DOUT_DRIVE_STR (R/W) [5] SAR_DIAG_MODE_EN (R/W) [4:3] SDO_DRIVE_STR (R/W) Table 63. Bit Descriptions for GENERAL_USER_CONFIG_2 Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved. 0x0 R/W 5 SAR_DIAG_MODE_EN Sets SPI to Read Back SAR Result on SDO. 0x0 R/W |
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