AD7770 datasheet(48/98 Pages) AD

48 / 98 page

Data Sheet

AD7770

Rev. C | Page 47 of 97

DIAGNOSTICS AND MONITORING

SELF DIAGNOSTICS ERROR

The AD7770 includes self diagnostic features to guarantee the

correct operation. If an error is detected, the ALERT pin is

pulled high to generate an external interruption to the controller.

In addition, the header of the Σ-Δ output data contains an alert

bit that informs the controller of a chip error (see the ADC

Conversion Output—Header and Data section).

Both the ALERT pin and bit (status header) are automatically

cleared if the error is no longer present. The errors related to

the SPI do not recover automatically; read back the appropriate

next SPI access after the bit is read back.

If an error detector is manually disabled, it does not generate an

internal error and, consequently, the register map or the

ALERT pin and bit are not triggered.

There are different sources of errors, as described in Table 29.

In pin control code, it is not possible to check the error source,

and some sources of error are not enabled. In SPI control mode,

check the source of an error by reading the appropriate register bit.

The STATUS_REG_x register bits identify the register that

generates an error, as summarized in Table 29.

Table 29. Register Error Source

Bit Name

ERR_LOC_GEN2

GEN_ERR_REG_2

ERR_LOC_GEN1

GEN_ERR_REG_1

ERR_LOC_CH7

CH7_ERR_REG

ERR_LOC_CH6

CH6_ERR_REG

ERR_LOC_CH5

CH5_ERR_REG

ERR_LOC_CH4

CH4_ERR_REG

ERR_LOC_CH3

CH3_ERR_REG

ERR_LOC_CH2

CH2_ERR_REG

ERR_LOC_CH1

CH1_ERR_REG

ERR_LOC_CH0

CH0_ERR_REG

ERR_LOC_SAT_CH6_7

CH6_7_SAT_ERR

ERR_LOC_SAT_CH4_5

CH4_5_SAT_ERR

ERR_LOC_SAT_CH2_3

CH2_3_SAT_ERR

ERR_LOC_SAT_CH0_1

CH0_1_SAT_ERR

In addition, the STATUS_REG_x registers have a bit that

indicates if any internal error bit is set, ERROR. This bit clears

if the error is no longer present and the register is read back.

The INIT_COMPLETE bit in the STATUS_REG_3 indicates

that the device is initialized correctly. This bit is not an error bit

but an indicator.

General Errors

MCLK Switch Error (SPI Control Mode)

After power-up, the AD7770 initiates a clocking handover

sequence to pass clocking control to the external oscillator, or

the CMOS clock. In SPI mode, if an error occurs in the handover,

the EXT_MCLK_SWITCH_ERR bit is set in the general error

If EXT_MCLK_SWITCH_ERR is set, the device is operating off

the internal oscillator, and is waiting for an appropriate external

clock.

To use a slow external clock (<265 kHz), set the CLK_QUAL_

DIS bit. Setting this bit also clears the error bit.

If the external clock is between 132 kHz and 265 kHz, depending

on the internal synchronization between the internal oscillator

and the external clock, the error may not trigger. However, it is

still recommended to set the CLK_QUAL_DIS bit.

If a slow clock is not in use and the error triggers, a reset is required.

Reset Detection

The AD7770 general error register contains a RESET_DETECTED

bit. This bit is asserted if a reset pulse is applied to the AD7770

and is cleared by reading the general error register. This bit

indicates that the power-on reset (POR) initialized correctly on the

device. In addition, this bit can detect an unexpected device reset

or glitch on the RESET pin. To reset this error signal in SPI control

mode, toggle the SYNC_IN pin or read from the general error

control mode, toggle the SYNC_IN pin.

Internal LDO Status

The AD7770 has three internal LDOs to regulate the internal

analog and digital supply rails. The LDOs have internal power

supply monitors. Internal comparators monitor and flag errors

with these supplies after they pass a predetermined limit.

The ALDO1_PSM_ERR, ALDO2_PSM_ERR, and DLDO_PSM_

ERR bits indicate either an LDO malfunction, or, if the LDOs

are bypassed, an incorrect external supply.

The internal analog and digital voltage monitors can be disabled

by appropriately selecting the LDO_PSM_TEST_EN bits.

Use the SAR ADC to verify the error.

Additionally, the levels of the internal monitors can be manually

triggered to check if the detector works correctly by appropriately

setting the LDO_PSM_TRIP_TEST_EN bits. These bits increase

the comparator window threshold above the LDO outputs,

forcing the comparator to trigger.

ROM and Memory Map CRC

If an error is found at power-up during the ROM verification,

or if the internal memory map is corrupted, the AD7770

generates an error and sets MEMMAP_CRC_ERR or ROM_

CRC_ERR, depending on the source of the error.

The checker can be disabled by clearing the MEMMAP_

CRC_TEST_EN and ROM_CRC_TEST_EN bits. The device

must be reset if any of these errors trigger.

AD7770 Datasheet(PDF) 48 Page - Analog Devices

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