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AD7770 Datasheet(PDF) 17 Page - Analog Devices

Part # AD7770
Description  8-Channel, 24-Bit, Simultaneous Sampling ADC
PDF  98 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7770 Datasheet(HTML) 17 Page - Analog Devices

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AD7770
Data Sheet
Rev. C | Page 16 of 97
Pin No.
Mnemonic
Type
Direction
Description
15
MODE2/GPIO2
Digital I/O
I/O
Mode 2 Input in Pin Control Mode (MODE2). See Table 14 for more details.
Configurable General-Purpose Input/Output 2 in SPI Control Mode (GPIO2). If
not in use, connect this pin to DGND or IOVDD.
16
MODE3/ALERT
Digital I/O
I/O
Mode 3 Input in Pin Control Mode (MODE3). See Table 14 for more details.
Alert Output in SPI Control Mode (ALERT).
17
CONVST_SAR
Digital input
Input
Σ-Δ Output Interface Selection Pin in Pin Control Mode. See Table 13 for more
details. This pin also functions as the start for the SAR conversion in SPI control
mode.
18
ALERT/CS
Digital input
Input
Alert Output in Pin Control Mode (ALERT).
Chip Select in SPI Control Mode (CS).
19
DCLK2/SCLK
Digital input
Input
DCLK Frequency Selection Pin 2 in Pin Control Mode (DCLK2). See Table 15 for
more details.
SPI Clock in SPI Control Mode (SCLK).
20
DCLK1/SDI
Digital input
Input
DCLK Frequency Selection Pin 1 in Pin Control Mode (DCLK1). See Table 15 for
more details.
SPI Data Input in SPI Control Mode (SDI). Connect this pin to DGND if the
device is configured in pin control mode with the SPI as the data output interface.
21
DCLK0/SDO
Digital output
Output
DCLK Frequency Selection Pin 0 in Pin Control Mode (DCLK0). See Table 15 for
more details.
SPI Data Output in SPI Control Mode (SDO).
22
DGND
Supply
Supply
Digital Ground.
23
DREGCAP
Supply
Output
Digital Low Dropout (LDO) Output. Decouple this pin to DGND with a 1 µF
capacitor.
24
IOVDD
Supply
Supply
Digital Levels Input/Output and Digital LDO (DLDO) Supply from 1.8 V to 3.6 V.
IOVDD must not be lower than DREGCAP.
25
DOUT3
Digital output
I/O
Data Output Pin 3. If the device is configured in daisy-chain mode, this pin
acts as an input pin. See the Daisy-Chain Mode section for more details.
26
DOUT2
Digital output
I/O
Data Output Pin 2. If the device is configured in daisy-chain mode, this pin
acts as an input pin. See the Daisy-Chain Mode section for more details.
27
DOUT1
Digital output
Output
Data Output Pin 1.
28
DOUT0
Digital output
Output
Data Output Pin 0.
29
DCLK
Digital output
Output
Data Output Clock.
30
DRDY
Digital output
Output
Data Output Ready Pin.
31
XTAL1
Clock
Input
Crystal 1 Input Connection. If CMOS is used as a clock source, tie this pin to
DGND. See Table 12 for more details.
32
XTAL2/MCLK
Clock
Input
Crystal 2 Input Connection (XTAL2). See Table 12 for more details.
CMOS Clock (MCLK). See Table 12 for more details.
33
START
Digital input
Input
Synchronization Pulse. This pin internally synchronizes an external START
asynchronous pulse with MCLK. The synchronize signal is shifted out by
the SYNC_OUT pin. If not in use, tie this pin to IOVDD. See the Phase Adjustment
section and the Digital Reset and Synchronization Pins section for more details.
34
SYNC_OUT
Digital output
Input
Synchronization Signal. This pin generates a synchronous pulse generated and
driven by hardware (via the START pin) or by software (GENERAL_USER_
CONFIG_2, Bit 0). If this pin is in use, it must be wired to the SYNC_IN pin. See
the Phase Adjustment section and the Digital Reset and Synchronization Pins
section for more details.
35
SYNC_IN
Digital input
Input
Reset for the Internal Digital Block and Synchronize for Multiple Devices. See
the Digital Reset and Synchronization Pins section for more details.
36
RESET
Digital input
Input
Asynchronous Reset Pin. This pin resets all registers to their default value. It is
recommended to generate a pulse on this pin after the device is powered up
because a slow slew rate in the supplies may generate an incorrect
initialization in the digital block.
37
AIN7+
Analog input
Input
Analog Input Channel 7, Positive.
38
AIN7−
Analog input
Input
Analog Input Channel 7, Negative.
39
AIN6+
Analog input
Input
Analog Input Channel 6, Positive.
40
AIN6−
Analog input
Input
Analog Input Channel 6, Negative.
41
REF2+
Reference
Input
Positive Reference Input 2 for Channel 4 to Channel 7, Typical at REF2− + 2.5V.



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