AD7770 datasheet(52/98 Pages) AD

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Data Sheet

AD7770

Rev. C | Page 51 of 97

Σ-∆ OUTPUT DATA

ADC CONVERSION OUTPUT—HEADER AND DATA

The AD7770 Σ-Δ conversion results are output on the DOUT0

to DOUT3 pins or over the SPI, depending on the selected

interface. If the DOUTx interface is selected, the AD7770 acts as

the master in the transmission. If the SPI is selected, the

controller is the master.

The DRDY signal indicates the end of conversion independent

of the interface selected to read back the Σ-Δ conversion. When

the SPI reads back the Σ-Δ conversion, if a new conversion is

completed (DRDY falling edge) before the previous conversion is

read back, the results from previous conversion are overwritten

and, consequently, the previous conversion data is corrupted.

For each channel, the width is 32 bits long: 8 bits for the header

and 24 bits for the Σ-Δ conversion, as shown in Figure 107.

ADC DATA N

N – 1

24-BITS

8-BITS

DOUTx

DRDY

HEADER N

Figure 107. ADC Output—8-Bit Header Plus 24-Bit Conversion Data

In pin control mode, the header is fixed to the CRC while in SPI

mode, and can be selected between CRC and error headers.

CRC Header

The CRC header is the header generated in pin control mode or

in SPI mode if DOUT_HEADER_FORMAT is set.

As shown in Figure 108, the header consists of an alert bit,

three bits for the ADC channel ID, as shown in Table 33, and

four bits for the CRC.

The chip error bit is set high if an error is detected in any channel,

as explained in the General Errors section. The alert bit remains

1 until the error disappears.

ALERT

CH_ID_2

CH_ID_1

CH_ID_0

CRC CRC CRC CRC

Figure 108. CRC Header

Table 33. Channel ID

Channel

CH_ID_2

CH_ID_1

CH_ID_0

The CRC generated is eight bits long; the 4 MSBs are placed on the

header for the first channel in the pairing and the 4 LSBs on the

header of the second channel in the pairing, as shown in Table 34.

If a channel is disabled, the 24-bit output data for this channel is

0x000000.

Table 34. 8-Bit CRC, Header Configuration (Channel 2)

ALERT

CRC7

CRC6

CRC5

CRC4

Table 35. 8-Bit CRC, Header Configuration (Channel 3)

ALERT

CRC3

CRC2

CRC1

CRC0

ERROR Header (SPI Control Mode)

In SPI control mode, the default header can be replaced by an error

header. If the Σ-Δ conversion is read back through the SPI, disable

the CRC by clearing the SPI_CRC_TEST_EN bit. If the DOUTx

interface is used, clear the DOUT_HEADER_

FORMAT bit.

The error header provides information of common error sources

specific for each channel, as shown in Table 36. Modulator and

filter errors are indicated even if the checker for these errors are

specifically disabled, as described in the Σ-Δ ADC Errors section.

Table 36. Status Header Output

Bits

Name

Description

Alert

This bit is set high if any of the enabled diagnostic functions have detected an error, including an

external clock not detected, a memory map bit flip, or an internal CRC error. This bit is not channel specific.

The bit clears if the error is no longer present.

[6:4]

CH_ID_[2:0]

These bits indicate which ADC channel the following conversion data came from (see Table 33).

RESET_DETECTED

This bit indicates if a reset condition occurs. This bit is not channel specific.

MODULATOR_SATURATE

This bit indicates that the modulator output is 20 consecutive 0s or 1s. The bit resets automatically

after the error is no longer present.

FILTER_SATURATE

This bit indicates that the filter output is out of bounds. The bit resets automatically after the error is

no longer present.

AIN_OV_UVERROR

This bit indicates that there is an AINx± overvoltage/undervoltage condition on the inputs. This bit is

set until the appropriate register is read back and the error is no longer present.

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