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AD7770 Datasheet(PDF) 95 Page - Analog Devices

Part # AD7770
Description  8-Channel, 24-Bit, Simultaneous Sampling ADC
PDF  98 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7770 Datasheet(HTML) 95 Page - Analog Devices

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AD7770
Data Sheet
Rev. C | Page 94 of 97
GENERAL ERRORS REGISTER 2 ENABLE
Address: 0x05C, Reset: 0x3C, Name: GEN_ERR_REG_2_EN
LDO PSM trip test enable
11: 11 - Run trip detect test on DRegCap.
10: 10 - Run trip detect test on AReg2Cap.
1: 01 - Run trip detect test on AReg1Cap.
0: 00 - No trip detect test enabled.
Reset detect enable
LDO PSM test EN
11:
on all LDOs.
11 - Run power supply monitor test
10:
on DRegCap.
10 - Run power supply monitor test
1:
on ARegxCap.
01 - Run power supply monitor test
0:
enabled.
00 - No power supply monitor test
0
0
1
0
2
1
3
1
4
0
5
1
6
0
7
0
[7:6] RESERVED
[1:0] LDO_PSM_TRIP_TEST_EN (R/W)
[5] RESET_DETECT_EN (R/W)
[3:2] LDO_PSM_test_EN (R/W)
[4] RESERVED
Table 136. Bit Descriptions for GEN_ERR_REG_2_EN
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
RESERVED
Reserved
0x0
R
5
RESET_DETECT_EN
Reset Detect Enable
0x1
R/W
4
RESERVED
Reserved
0x1
R/W
[3:2]
LDO_PSM_TEST_EN
LDO PSM Test EN
0x3
R/W
0
00—no power supply monitor test enabled
1
01—run power supply monitor test on AREGxCAP
10
10—run power supply monitor test on DREGCAP
11
11—run power supply monitor test on all LDOs
[1:0]
LDO_PSM_TRIP_TEST_EN
LDO PSM Trip Test Enable
0x0
R/W
0
00—no trip detect test enabled
1
01—run trip detect test on AREG1CAP
10
10—run trip detect test on AREG2CAP
11
11—run trip detect test on DREGCAP
ERROR STATUS REGISTER 1
Address: 0x05D, Reset: 0x00, Name: STATUS_REG_1
An error specific to CH0_ERR_REG
is active
Set high if any error bit is high
An error specific to CH1_ERR_REG
is active
An error specific to CH4_ERR_REG
is active
An error specific to CH2_ERR_REG
is active
An error specific to CH3_ERR_REG
is active
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED
[0] ERR_LOC_CH0 (R)
[5] CHIP_ERROR (R)
[1] ERR_LOC_CH1 (R)
[4] ERR_LOC_CH4 (R)
[2] ERR_LOC_CH2 (R)
[3] ERR_LOC_CH3 (R)
Table 137. Bit Descriptions for STATUS_REG_1
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
RESERVED
Reserved
0x0
R
5
CHIP_ERROR
Set this bit high if any error bit is high
0x0
R
4
ERR_LOC_CH4
An error specific to CH4_ERR_REG is active
0x0
R
3
ERR_LOC_CH3
An error specific to CH3_ERR_REG is active
0x0
R
2
ERR_LOC_CH2
An error specific to CH2_ERR_REG is active
0x0
R
1
ERR_LOC_CH1
An error specific to CH1_ERR_REG is active
0x0
R
0
ERR_LOC_CH0
An error specific to CH0_ERR_REG is active
0x0
R



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