AD7770 datasheet(78/98 Pages) AD

78 / 98 page

Data Sheet

AD7770

Rev. C | Page 77 of 97

CHANNEL 0 GAIN LOWER BYTE REGISTER

Address: 0x021, Reset: 0x00, Name: CH0_GAIN_LOWER_BYTE

Combined gain register Channel 0

[7:0] CH0_GAIN_ALL[7:0] (R/W)

Table 77. Bit Descriptions for CH0_GAIN_LOWER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH0_GAIN_ALL[7:0]

Combined Gain Register Channel 0

0x0

R/W

CHANNEL 1 OFFSET UPPER BYTE REGISTER

Address: 0x022, Reset: 0x00, Name: CH1_OFFSET_UPPER_BYTE

Combined offset register Channel 1

[7:0] CH1_OFFSET_ALL[23:16] (R/W)

Table 78. Bit Descriptions for CH1_OFFSET_UPPER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH1_OFFSET_ALL[23:16]

Combined Offset Register Channel 1

0x0

R/W

CHANNEL 1 OFFSET MIDDLE BYTE REGISTER

Address: 0x023, Reset: 0x00, Name: CH1_OFFSET_MID_BYTE

Combined offset register Channel 1

[7:0] CH1_OFFSET_ALL[15:8] (R/W)

Table 79. Bit Descriptions for CH1_OFFSET_MID_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH1_OFFSET_ALL[15:8]

Combined Offset Register Channel 1

0x0

R/W

CHANNEL 1 OFFSET LOWER BYTE REGISTER

Address: 0x024, Reset: 0x00, Name: CH1_OFFSET_LOWER_BYTE

Combined offset register Channel 1

[7:0] CH1_OFFSET_ALL[7:0] (R/W)

Table 80. Bit Descriptions for CH1_OFFSET_LOWER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH1_OFFSET_ALL[7:0]

Combined Offset Register Channel 1

0x0

R/W

AD7770 Datasheet(PDF) 78 Page - Analog Devices

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