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AD7771 Datasheet(PDF) 41 Page - Analog Devices |
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AD7771 Datasheet(HTML) 41 Page - Analog Devices |
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41 / 99 page ![]() AD7771 Data Sheet Rev. 0 | Page 40 of 98 Table 14. Pin Control Mode Options Pin State Decimation Rate Power Mode PGA Gain Channel Reference Source Filter MODE3 MODE2 MODE1 MODE0 Channel 0 to Channel 3 Channel 4 to Channel 7 0 0 0 0 16 High resolution 1 1 External Sinc5 0 0 0 1 16 High resolution 1 4 External Sinc5 0 0 1 0 32 High resolution 1 1 External Sinc5 0 0 1 1 32 High resolution 1 4 External Sinc5 0 1 0 0 64 High resolution 1 1 External Sinc5 0 1 0 1 64 High resolution 1 4 External Sinc5 0 1 1 0 128 High resolution 1 1 External Sinc5 0 1 1 1 128 High resolution 1 4 External Sinc5 1 0 0 0 256 High resolution 1 1 External Sinc5 1 0 0 1 16 High resolution 1 1 Internal Sinc5 1 0 1 0 32 High resolution 1 1 Internal Sinc5 1 0 1 1 64 High resolution 1 1 Internal Sinc5 1 1 0 0 16 Low power 1 1 External Sinc5 1 1 0 1 32 Low power 1 1 External Sinc5 1 1 1 0 64 Low power 1 1 External Sinc3 1 1 1 1 32 Low power 1 1 External Sinc3 Table 15. DCLKx Selection for Pin Control Mode State DCLK2/SCLK DCLK1/SDI DCLK0/SDO MCLK Divider 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 |
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