AD7771 datasheet(81/99 Pages) AD

81 / 99 page

AD7771

Data Sheet

Rev. 0 | Page 80 of 98

CHANNEL 2 GAIN UPPER BYTE REGISTER

Address: 0x02B, Reset: 0x00, Name: CH2_GAIN_UPPER_BYTE

Com bined gain regis ter Channel 2

[7:0] CH2_GAIN_ALL[23:16] (R/W)

Table 86. Bit Descriptions for CH2_GAIN_UPPER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH2_GAIN_ALL[23:16]

Combined Gain Register Channel 2

0x0

R/W

CHANNEL 2 GAIN MIDDLE BYTE REGISTER

Address: 0x02C, Reset: 0x00, Name: CH2_GAIN_MID_BYTE

Com bined gain regis ter Channel 2

[7:0] CH2_GAIN_ALL[15:8] (R/W)

Table 87. Bit Descriptions for CH2_GAIN_MID_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH2_GAIN_ALL[15:8]

Combined Gain Register Channel 2

0x0

R/W

CHANNEL 2 GAIN LOWER BYTE REGISTER

Address: 0x02D, Reset: 0x00, Name: CH2_GAIN_LOWER_BYTE

Com bined gain regis ter Channel 2

[7:0] CH2_GAIN_ALL[7:0] (R/W)

Table 88. Bit Descriptions for CH2_GAIN_LOWER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH2_GAIN_ALL[7:0]

Combined Gain Register Channel 2

0x0

R/W

CHANNEL 3 OFFSET UPPER BYTE REGISTER

Address: 0x02E, Reset: 0x00, Name: CH3_OFFSET_UPPER_BYTE

Com bined offs et regis ter Channel 3

[7:0] CH3_OFFSET_ALL[23:16] (R/W)

Table 89. Bit descriptions for CH3_OFFSET_UPPER_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH3_OFFSET_ALL[23:16]

Combined Offset Register Channel 3

0x0

R/W

CHANNEL 3 OFFSET MIDDLE BYTE REGISTER

Address: 0x02F, Reset: 0x00, Name: CH3_OFFSET_MID_BYTE

Com bined offs et regis ter Channel 3

[7:0] CH3_OFFSET_ALL[15:8] (R/W)

Table 90. Bit Descriptions for CH3_OFFSET_MID_BYTE

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH3_OFFSET_ALL[15:8]

Combined Offset Register Channel 3

0x0

R/W

AD7771 Datasheet(PDF) 81 Page - Analog Devices

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