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AD7771 Datasheet(PDF) 42 Page - Analog Devices

Part # AD7771
Description  8-Channel, 24-Bit, Simultaneous Sampling ADC
PDF  99 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7771 Datasheet(HTML) 42 Page - Analog Devices

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Data Sheet
AD7771
Rev. 0 | Page 41 of 98
ADC
DATA
SERIAL
INTERFACE
SPI
CONTROL
INTERFACE
FPGA
OR
DSP
AVDD 3.3V
EXTERNAL
REFERENCE
AVSSx
AVSSx
AIN7+
AIN7–
AIN0+
AIN0–
PGA
VCM
AVDD1x
BUFFER
BUFFER
AD7771
DREGCAP
CONVST_SAR
MODE3
TO
MODE0
REFx+
REFx–
REF_OUT
AVDD4
AVSSx
AVSSx
AVDD2x
AVDD3.3V
AVDD3.3V
IOVDD 2V TO 3.6V
AVSSx
AREGxCAP
AVSSx
AVSSx
IOVDD
24-BIT
Σ-Δ
ADC
SINC3/SINC5
SRC
SYNC_IN
DRDY
SYNC_OUT
START
RESET
DCLK
CS
SCLK
SDO
CLK_SEL
XTAL2
DCLK2
TO
DCLK0
XTAL1
DOUT0
DOUT1
SPI/SPORT
SLAVE
INTERFACE
DOUT2
DOUT3
SPI
MASTER
INTERFACE
PGA
VCM
SDI
FORMAT1
AND
FORMAT0
CLOCK
SOURCE
Figure 114. Pin Control Mode Connection Diagram with External Reference
ADC
DATA
SERIAL
INTERFACE
SPI
CONTROL
INTERFACE
FPGA
OR
DSP
AVDD 3.3V
AVSSx
AVSSx
AIN7+
AIN7–
AIN0+
AIN0–
PGA
VCM
AVDD1x
BUFFER
FULL BUFFER
BUFFER
AD7771
DREGCAP
CONVST_SAR
GPIO2
TO
GPIO0
REFx+
REFx–
REF_OUT AVDD4
AVSSx
AVDD2x
AVDD3.3V
IOVDD 2V TO 3.6V
AVSSx
AREGxCAP
AVSSx
AVSSx
IOVDD
AUXAIN+
AUXAIN–
24-BIT
Σ-Δ
ADC
12-BIT
SAR ADC
MUX
DIAGNOSTIC
INPUTS
SINC3/SINC5
SRC
SYNC_IN
DRDY
SYNC_OUT
START
RESET
DCLK
CS
SCLK
SDO
SDI
CLK_SEL
FORMAT0
XTAL2
FORMAT1
IOVDD
IOVDD
XTAL1
DOUT0
DOUT1
SPI/SPORT
SLAVE
INTERFACE
DOUT2
DOUT3
SPI
MASTER
INTERFACE
PGA
VCM
CLOCK
SOURCE
Figure 115. SPI Control Mode Connection Diagram with Internal Reference



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