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AD7771 Datasheet(PDF) 56 Page - Analog Devices |
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AD7771 Datasheet(HTML) 56 Page - Analog Devices |
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56 / 99 page ![]() Data Sheet AD7771 Rev. 0 | Page 55 of 98 SRC Bandwidth The sinc3 and sinc5 filters architecture allows the user to select a noninteger value as the decimation range This versatility means that the filter notches must be adjusted dynamically: two notches (sinc3) or four notches (sinc5) at the variable frequency, and one fixed notch to remove the PGA chopping tone. Consequently, the traditional formula for the −0.1 dB and −3 dB bandwidth must be adjusted depending on the selected decimation rate. The bandwidth transfer function is not linear but can be approximated by using a linear function. Figure 126 to Figure 129 show the correction factor for the −0.1 dB and −3 dB bandwidth, respectively. In low power mode, the offset must be divided by 4. For example, for sinc5 when the ODR = 1000 SPS, the −0.1 dB point is BW = 0.0377 × 1000 + 4 355 . 49 = 50.03 Hz 7 0 1 2 3 4 5 6 0 100 50 ODR (kHz) y = 0.049x + 120.41 Figure 126. −0.1 dB Correction Factor, Sinc3 Filter Enabled 6 0 1 2 3 4 5 0 100 50 ODR (kHz) y = 0.0377x + 49.355 Figure 127. −0.1 dB Correction Factor, Sinc5 Filter Enabled 40 0 5 10 15 20 25 30 35 0 100 50 ODR (kHz) y = 0.2653x + 634.03 Figure 128. −3 dB Correction Factor, Sinc3 Filter Enabled 30 0 5 10 15 20 25 0 100 50 ODR (kHz) y = 0.2053x + 263.94 Figure 129. −3 dB Correction Factor, Sinc5 Filter Enabled SRC Group Delay The SRC group delay depends on the selected ODR and is defined by the following equation: SRC Group Delay = ODR N SRC N SRC PM × + _ _ where: PM is a constant equal to 8. SRC_N is the integer value of the programmed ODR. ODR is the programmed output data rate. When using the sinc5 filter, the equation that defines the group delay is SRC Group Delay = ODR N SRC N SRC PM × × + _ _ 2 The latency is the contribution of the group delay and the calibration time. Latency = Group Delay + tCAL In high resolution mode, the calibration delay is defined as 62 × tMCLK, with a maximum error of 2 × tMCLK. In low power mode, the calibration delay is defined as 121 × tMCLK, with a maximum error of 4 × tMCLK. tMCLK is the modulator period and is 488 ns in high resolution mode and 1.9 µs in low power mode. |
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