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AD7771 Datasheet(PDF) 57 Page - Analog Devices |
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AD7771 Datasheet(HTML) 57 Page - Analog Devices |
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57 / 99 page  AD7771 Data Sheet Rev. 0 | Page 56 of 98 Settling Time The settling time is defined by the contribution of all the internal stages, the filter delay, and the block calibration. When using the sinc3 filter option, the filter delay is defined as 3/ODR. In some extreme cases, such as when an external pulse is applied, this value may increase to 4/ODR. If using the sinc5 filter, the filter delay is defined as 5/ODR, or 6/ODR for extreme cases. DATA OUTPUT INTERFACE The Σ-Δ output data interface is defined by the CONVST_SAR, FORMAT0, and FORMAT1 pins in pin control mode at power-up. The FORMATx pins cannot be changed dynamically. Table 14 shows the available options for pin control mode. If the device is configured in SPI control mode, the SPI_SLAVE_MODE_ EN bit enables the SPI to transmit the Σ-Δ ADC conversion results, as shown in Table 22. DOUT3 to DOUT0 Data Interface Standalone Mode In standalone mode, the AD7771 interface acts as a master. There are three different DOUT configurations, configurable through the FORMATx pins in pin control mode, as shown in Figure 130 through Figure 132, or via the DOUT_FORMAT bits, Bits[7:6], in SPI control mode, as described in Table 36. Figure 133, Figure 134, and Figure 135 show the expected data outputs for different DOUTx output modes. Table 36. DOUTx Channels DOUT_FORMAT Bits/ FORMATx Pins Number of DOUTx Lines Enabled Associated Channels 00 4 DOUT0—Channel 0 and Channel 1 DOUT1—Channel 2 and Channel 3 DOUT2—Channel 4 and Channel 5 DOUT3—Channel 6 and Channel 7 01 2 DOUT0—Channel 0, Channel 1, Channel 2, and Channel 3 DOUT1—Channel 4, Channel 5, Channel 6, and Channel 7 10 or 11 1 DOUT0—Channel 0, Channel 1, Channel 2, Channel 3, Channel 4, Channel 5, Channel 6, and Channel 7 DOUT0 DOUT1 DOUT2 DOUT3 DCLK DRDY FORMAT1 DAISY-CHAINING IS NOT POSSIBLE IN THIS FORMAT FORMAT0 AD7771 CH 0 CH 1 CH 0 CH 1 CH 0 CH 1 CH 0 CH 1 DGND DOUT0: CH 0, CH 1 DOUT1: CH 2, CH 3 DOUT2: CH 4, CH 5 DOUT3: CH 6, CH 7 0 0 00 Figure 130. FORMATx Pin Configuration—FORMAT0 = 0, FORMAT1 = 0 DOUT0 DOUT1 DCLK DRDY FORMAT1 IOVDD DAISY-CHAINING IS POSSIBLE IN THIS FORMAT DGND FORMAT0 CH 0, CH 1, CH 2, CH 3 OUTPUT ON DOUT0 CH 4, CH 5, CH 6, CH 7 OUTPUT ON DOUT1 01 1 0 AD7771 CH 4 CH 5 CH 6 CH 7 CH 0 CH 1 CH 2 CH 3 Figure 131. FORMATx Pin Configuration—FORMAT0 = 1, FORMAT1 = 0 DOUT0 DCLK DRDY FORMAT1 IOVDD DAISY-CHAINING IS POSSIBLE IN THIS FORMAT DGND FORMAT0 CH 0 TO CH 7 OUTPUT ON DOUT0 10 0 1 AD7771 CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 Figure 132. FORMATx Pin Configuration—FORMAT0 = 0, FORMAT1 = 1 |
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