AD9689 datasheet(103/134 Pages) AD

103 / 134 page

Data Sheet

AD9689

Rev. A | Page 103 of 134

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset Access

0x0129 SYSREF Status 2

[7:4] Reserved

Reserved.

0x0

[3:0] Clock divider phase when

SYSREF± was captured

SYSREF divider phase. Represents the phase of the divider

when SYSREF± was captured.

0x0

0000

In phase.

0001

SYSREF± is ½ cycle delayed from clock.

0010

SYSREF± is 1 cycle delayed from clock.

0011

SYSREF± is 1½ input clock cycles delayed.

0100

SYSREF± is 2 input clock cycles delayed.

…

1111

SYSREF± is 7½ input clock cycles delayed.

0x012A SYSREF Status 3

[7:0] SYSREF counter, Bits[7:0]

increments when a

SYSREF± is captured

SYSREF count. Running counter that increments whenever a

SYSREF± event is captured. Reset by Register 0x0120, Bit 6. Wraps

around at 255. Read these bits only when Register 0x0120, Bits[2:1]

are set to disabled.

0x0

0x01FF Chip sync mode

[7:1] Reserved

Reserved.

0x0

Synchronization mode

0x0

R/W

JESD204B synchronization mode. The SYSREF signal resets all

internal clock dividers. Use this mode when synchronizing

multiple chips as specified in the JESD204B standard. If the

phase of any of the dividers must change, the JESD204B link

goes down.

Timestamp mode. The SYSREF signal does not reset internal

clock dividers. In this mode, the JESD204B link and the signal

monitor are not affected by the SYSREF signal. The SYSREF

signal timestamps a sample when it passes through the ADC

and is used as a control bit in the JESD204B output word.

Chip Operating Mode Control Registers

Table 48.

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset Access

0x0200 Chip mode

[7:6] Reserved

Reserved.

0x0

R/W

Chip Q ignore

Chip real (I) only selection.

0x0

R/W

Both real (I) and complex (Q) selected.

Only real (I) selected; complex (Q) is ignored.

Reserved

Reserved.

0x0

[3:0] Chip application mode

0x0

R/W

0000

Full bandwidth mode (default).

0001

One DDC mode (DDC0 only).

0010

Two DDC mode (DDC0 and DDC1 only).

0011

Four DDC mode (DDC0, DDC1, DDC2, and DDC3).

0x0201 Chip decimation

ratio

[7:4] Reserved

Reserved.

0x0

[3:0] Chip decimation ratio

Chip decimation ratio.

0x0

R/W

0000

Full sample rate (decimate by 1, DDCs are bypassed).

0001

Decimate by 2.

1000

Decimate by 3.

0010

Decimate by 4.

0101

Decimate by 5.

1001

Decimate by 6.

0011

Decimate by 8.

0110

Decimate by 10.

1010

Decimate by 12.

0111

Decimate by 15.

0100

Decimate by 16.

1101

Decimate by 20.

1011

Decimate by 24.

1110

Decimate by 30.

1111

Decimate by 40.

1100

Decimate by 48.

AD9689 Datasheet(PDF) 103 Page - Analog Devices

AD9689 Datasheet(HTML) 103 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL