AD7682 datasheet(31/35 Pages) AD

31 / 35 page

Data Sheet

AD7682/AD7689

Rev. H | Page 31 of 35

READ/WRITE SPANNING CONVERSION WITHOUT

A BUSY INDICATOR

This mode is used when the AD7682/AD7689 are connected to

any host using an SPI, serial port, or FPGA. The connection

diagram is shown in Figure 42, and the corresponding timing is

given in Figure 43. For the SPI, the host must use CPHA =

CPOL = 0. Reading/writing spanning conversion is shown,

which covers all three modes detailed in the Digital Interface

section. For this mode, the host must generate the data transfer

based on the conversion time. For an interrupt driven transfer

that uses a busy indicator, refer to the Read/Write Spanning

Conversion with a Busy Indicator section.

A rising edge on CNV initiates a conversion, forces SDO to

high impedance, and ignores data present on DIN. After a

conversion initiates, it continues until completion, irrespective

of the state of CNV. CNV must be returned high before the safe

data transfer time (tDATA), and held high beyond the conversion

time (tCONV) to avoid generation of the busy signal indicator.

After the conversion is complete, the AD7682/AD7689 enter

the acquisition phase and power-down. When the host brings

CNV low after tCONV (maximum), the MSB enables on SDO. The

host also must enable the MSB of the CFG register at this time

(if necessary) to begin the CFG update. While CNV is low, both

a CFG update and a data readback take place. The first 14 SCK

rising edges are used to update the CFG, and the first 15 SCK

falling edges clock out the conversion results starting with

MSB − 1. The restriction for both configuring and reading is

that they both must occur before the tDATA time of the next

conversion elapses. All 14 bits of CFG[13:0] must be written or

they are ignored. In addition, if the 16-bit conversion result is

not read back before tDATA elapses, it is lost.

The SDO data is valid on both SCK edges. Although the rising

edge can capture the data, a digital host using the SCK falling

edge allows a faster reading rate, provided it has an acceptable

hold time. After the 16th (or 30th) SCK falling edge, or when

CNV goes high (whichever occurs first), SDO returns to high

impedance.

If CFG readback is enabled, the CFG register associated with

the conversion result is read back MSB first following the LSB of

the conversion result. A total of 30 SCK falling edges is required

to return SDO to high impedance if this is enabled.

MISO

MOSI

SCK

CNV

FOR SPI USE CPHA = 0, CPOL = 0.

SCK

SDO

DIN

AD7682/

AD7689

DIGITAL HOST

Figure 42. Connection Diagram for the AD7682/AD7689 Without a Busy Indicator

UPDATE (n)

CFG/SDO

UPDATE (n + 1)

CFG/SDO

ACQUISITION (n)

ACQUISITION

(n - 1)

MSB

BEGIN DATA (n – 1)

BEGIN CFG (n + 1)

CFG

MSB

SEE NOTE

NOTES

1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF

15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.

29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.

ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.

16/

CONVERSION (n)

END DATA (n – 1)

END CFG (n + 1)

CFG

LSB

CONV

LSB

SCK

CNV

DIN

SDO

16/

CONVERSION (n – 1)

END DATA (n – 2)

END CFG (n)

CFG

LSB

CONV

DATA

CNVH

DATA

DIS

DSDO

HSDO

HDIN

SDIN

CLSCK

SCK

SCKH

SCKL

DIS

CONV

LSB

ACQ

CYC

(QUIET

TIME)

(QUIET

TIME)

EOC

RETURN CNV HIGH

FOR NO BUSY

RETURN CNV HIGH

FOR NO BUSY

Figure 43. Serial Interface Timing for the AD7682/AD7689 Without a Busy Indicator

AD7682 Datasheet(PDF) 31 Page - Analog Devices

AD7682 Datasheet(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Datasheet Download

Link URL