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CCG4 Datasheet(PDF) 20 Page - Cypress Semiconductor

Part # CCG4
Description  USB Type-C Port Controller
PDF  35 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CCG4 Datasheet(HTML) 20 Page - Cypress Semiconductor

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Document Number: 001-98440 Rev. *J
Page 20 of 35
EZ-PD™ CCG4
Device-Level Specifications
All specifications are valid for –40 °C
 TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 3.0 V to 5.5 V,
except where noted.
Table 9. DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID.PWR#1
VDDD
Power supply input voltage
2.7
–
5.5
V
UFP applications
SID.PWR#1_A
VDDD
Power supply input voltage
3.15
–
5.5
V
DFP/DRP applications
SID.PWR#26
V5V_P1,
V5V_P2
Power supply input voltage
4.85
–
5.5
V
–
PWR#13
VDDIO
GPIO power supply
1.71
–
5.5
V
–
SID.PWR#24
VCCD
Output voltage (for core logic)
–
1.8
–
V
–
SID.PWR#15
CEFC
External regulator voltage bypass
on VCCD
80
100
120
nF
X5R ceramic or better
SID.PWR#16
CEXC
Power supply decoupling capacitor
on VDDD
0.8
1
–
µF
X5R ceramic or better
SID.PWR#27
CEXV
Power supply decoupling capacitor
on V5V_P1 and V5V_P2
–0.1
–
µF
X5R ceramic or better
Active Mode, VDDD = 2.7 to 5.5 V. Typical values measured at VDD = 3.3 V.
SID.PWR#4
IDD12
Supply current
–
10
–
mA
V5V_P1 and V5V_P2 = 5 V,
TA = 25 °C,
CC I/O IN Transmit or Receive,
no I/O sourcing current, CPU at
24 MHz, two PD ports active
Sleep Mode, VDDD = 2.7 to 5.5 V
SID25A
IDD20A
I2C wakeup
WDT ON
IMO at 48 MHz
–2.5
4.0
mA
VDDD = 3.3 V, TA = 25 °C, all
blocks except CPU are ON, CC
I/O ON, no I/O sourcing current
Deep Sleep Mode, VDDD = 2.7 to 3.6 V (Regulator on)
SID34
IDD29
VDDD = 2.7 to 3.6 V
I2C wakeup and WDT ON
–80
–
µAVDDD = 3.3 V, TA = 25 °C
SID_DS
IDD_DS
VDDD = 2.7 to 3.6 V
CC wakeup ON
–2.5
–
µA
Power source = VDDD, Type-C
not attached, CC enabled for
wakeup, RP disabled
SID_DS1
IDD_DS1
VDDD = 2.7 to 3.6 V
CC wakeup ON
–100
–
µA
Power source = VDDD, Type-C
not attached, CC enabled for
wakeup, RP and RD connected
at 70 ms intervals by CPU. RP,
RD connection should be
enabled for both PD ports.
XRES Current
SID307
IDD_XR
Supply current while XRES
asserted
–
1
10
µA–



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