CS5530A datasheet(28/259 Pages) NSC

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Revision 1.1

Signal Definitions (Continued)

2.2.5

ISA Bus Interface

Signal Name

No.

Type

Description

SA_LATCH/

SA_DIR

AD15

Limited ISA Mode: System Address Latch

This signal is used to latch the destination address, which is multiplexed on

bits [15:0] of the SA/SD bus.

ISA Master Mode: System Address Direction

Controls the direction of the external 5.0V tolerant transceiver on bits [15:0]

of the SA bus. When low, the SA bus is driven out. When high, the SA bus is

driven into the CS5530A by the external transceiver.

SA_OE#/

FP_DATA16

Limited ISA Mode: Flat Panel Data Port Line 16

Refer to Section 2.2.11 "Display Interface" on page 35 for this signal’s defini-

tion.

ISA Master Mode: System Address Transceiver Output Enable

Enables the external transceiver on bits [15:0] of the SA bus.

MASTER#/

FP_DATA17

Limited ISA Mode: Flat Panel Data Port Line 17

Refer to Section 2.2.11 "Display Interface" on page 35 for this signal’s defini-

tion.

ISA Master Mode: Master

The MASTER# input asserted indicates an ISA bus master is driving the ISA

bus.

SA23/GPIO7

AF23

I/O

Limited ISA Mode: System Address Bus Lines 23 through 20 or

General Purpose I/Os 7 through 4

These pins can function either as the upper four bits of the SA bus or as

general purpose I/Os. Programming is done through F0 Index 43h, bits 6

and 2.

Refer to Section 2.2.9 "Game Port and General Purpose I/O Interface" on

page 33 for further details when used as GPIOs.

SA22/GPIO6

AE23

SA21/GPIO5

AC21

SA20/GPIO4

AD22

ISA Master Mode: System Address Bus Lines 23 through 20

The pins function only as the four MSB (most significant bits) of the SA bus.

SA[19:16]

AD10,

AE11,

AF12,

AD11

I/O

(PU)

System Address Bus Lines 19 through 16

Refer to SA[15:0] signal description.

SA[15:0]/SD[15:0]

Refer

Table

2-3

I/O

(PU)

Limited ISA Mode: System Address Bus / System Data Bus

This bus carries both the addresses and data for all ISA cycles. Initially, the

address is placed on the bus and then SA_LATCH is asserted in order for

external latches to latch the address. At some time later, the data is put on

the bus, for a read, or the bus direction is changed to an input, for a write.

Pins designated as SA/SD[15:0] are internally connected to a 20-kohm pull-

up resistor.

ISA Master Mode: System Data Bus

These pins perform only as SD[15:0] and pins FP_DATA[15:0] take on the

functions of SA[15:0].

Pins designated as SA/SD[15:0] are internally connected to a 20-kohm pull-

up resistor.

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